参数资料
型号: ATMEGA1284P-PU
厂商: Atmel
文件页数: 12/160页
文件大小: 0K
描述: MCU AVR 128K ISP FLASH 40-PDIP
产品培训模块: MCU Product Line Introduction
megaAVR Introduction
标准包装: 10
系列: AVR® ATmega
核心处理器: AVR
芯体尺寸: 8-位
速度: 20MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 128KB(64K x 16)
程序存储器类型: 闪存
EEPROM 大小: 4K x 8
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 40-DIP(0.600",15.24mm)
包装: 管件
产品目录页面: 614 (CN2011-ZH PDF)
配用: ATSTK600-RC05-ND - STK600 ROUTING CARD AVR
ATSTK600-TQFP44-ND - STK600 SOCKET/ADAPTER 44-TQFP
ATSTK600-ND - DEV KIT FOR AVR/AVR32
109
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
15.9.6
TIMSK0 – Timer/Counter Interrupt Mask Register
Bits 7:3 – Reserved
These bits are reserved and will always read as zero.
Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, that is, when the OCF0B bit is set in the
Timer/Counter Interrupt Flag Register – TIFR0.
Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter0 occurs, that is, when the OCF0A bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR0.
Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, that is, when the TOV0 bit is set in the Timer/Counter 0 Inter-
rupt Flag Register – TIFR0.
15.9.7
TIFR0 – Timer/Counter 0 Interrupt Flag Register
Bits 7:3 – Reserved
These bits are reserved and will always read as zero.
Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in
OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the cor-
responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),
and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
Bit 1 – OCF0A: Timer/Counter 0 Output Compare A Match Flag
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data
in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor-
responding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),
and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.
Bit
7
6
5
4
3
2
1
0
OCIE0B
OCIE0A
TOIE0
TIMSK0
Read/Write
RRRR
R
R/W
Initial Value
0
Bit
7
6
543210
–OCF0B
OCF0A
TOV0
TIFR0
Read/Write
RRRRR
R/W
Initial Value
0
000000
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