参数资料
型号: ATMEGA1284P-PU
厂商: Atmel
文件页数: 40/160页
文件大小: 0K
描述: MCU AVR 128K ISP FLASH 40-PDIP
产品培训模块: MCU Product Line Introduction
megaAVR Introduction
标准包装: 10
系列: AVR® ATmega
核心处理器: AVR
芯体尺寸: 8-位
速度: 20MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 128KB(64K x 16)
程序存储器类型: 闪存
EEPROM 大小: 4K x 8
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 40-DIP(0.600",15.24mm)
包装: 管件
产品目录页面: 614 (CN2011-ZH PDF)
配用: ATSTK600-RC05-ND - STK600 ROUTING CARD AVR
ATSTK600-TQFP44-ND - STK600 SOCKET/ADAPTER 44-TQFP
ATSTK600-ND - DEV KIT FOR AVR/AVR32
134
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
Table 16-3 on page 134 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to
the fast PWM mode.
Note:
1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. In
this case the compare match is ignored, but the set or clear is done at BOTTOM. See Section
Table 16-4 on page 134 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to
the phase correct or the phase and frequency correct, PWM mode.
Note:
1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. See
Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 16-5 on page 135. Modes of operation supported by the
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode,
and three types of Pulse Width Modulation (PWM) modes. (See Section “16.10” on page 124).
Table 16-3.
Compare Output mode, fast PWM
COMnA1/COMnB1
COMnA0/COMnB0
Description
0
Normal port operation, OCnA/OCnB disconnected.
01
WGMn3:0 = 14 or 15: Toggle OC1A on Compare
Match, OC1B disconnected (normal port operation).
For all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
10
Clear OCnA/OCnB on Compare Match, set
OCnA/OCnB at BOTTOM (non-inverting mode)
11
Set OCnA/OCnB on Compare Match, clear
OCnA/OCnB at BOTTOM (inverting mode)
Table 16-4.
Compare Output mode, phase correct and phase and frequency correct PWM (1).
COMnA1/COMnB1
COMnA0/COMnB0
Description
0
Normal port operation, OCnA/OCnB disconnected.
01
WGMn3:0 = 9 or 11: Toggle OCnA on Compare
Match, OCnB disconnected (normal port operation).
For all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
10
Clear OCnA/OCnB on Compare Match when up-
counting. Set OCnA/OCnB on Compare Match when
downcounting.
11
Set OCnA/OCnB on Compare Match when up-
counting. Clear OCnA/OCnB on Compare Match
when downcounting.
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