参数资料
型号: ATMEGA645V-8MUR
厂商: Atmel
文件页数: 11/85页
文件大小: 0K
描述: MCU AVR 64KB FLASH 8MHZ 64QFN
产品培训模块: megaAVR Introduction
标准包装: 4,000
系列: AVR® ATmega
核心处理器: AVR
芯体尺寸: 8-位
速度: 8MHz
连通性: SPI,UART/USART,USI
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 53
程序存储器容量: 64KB(32K x 16)
程序存储器类型: 闪存
EEPROM 大小: 2K x 8
RAM 容量: 4K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-VFQFN 裸露焊盘
包装: 带卷 (TR)
其它名称: ATMEGA645V-8MUR-ND
ATMEGA645V-8MURTR
19
2570N–AVR–05/11
ATmega325/3250/645/6450
8.2
SRAM Data Memory
Figure 8-2 on page 19 shows how the Atmel ATmega325/3250/645/6450 SRAM Memory is
organized.
The Atmel ATmega325/3250/645/6450 is a complex microcontroller with more peripheral units
than can be supported within the 64 locations reserved in the Opcode for the IN and OUT
instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
The lower 2304/4352 data memory locations address both the Register File, the I/O memory,
Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register
File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory,
and the next 2048/4096 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and
the 2,048 bytes of internal data SRAM in the Atmel ATmega325/3250/645/6450 are all accessi-
ble through all these addressing modes. The Register File is described in “General Purpose
Figure 8-2.
Data Memory Map
8.2.1
Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
CPU cycles as described in Figure 8-3.
32 Registers
64 I/O Registers
Internal SRAM
(2048 x 8)/
(4096 x 8)
0x0000 - 0x001F
0x0020 - 0x005F
0x08FF/0x10FF
0x0060 - 0x00FF
Data Memory
160 Ext I/O Reg.
0x0100
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