参数资料
型号: ATMEGA645V-8MUR
厂商: Atmel
文件页数: 16/85页
文件大小: 0K
描述: MCU AVR 64KB FLASH 8MHZ 64QFN
产品培训模块: megaAVR Introduction
标准包装: 4,000
系列: AVR® ATmega
核心处理器: AVR
芯体尺寸: 8-位
速度: 8MHz
连通性: SPI,UART/USART,USI
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 53
程序存储器容量: 64KB(32K x 16)
程序存储器类型: 闪存
EEPROM 大小: 2K x 8
RAM 容量: 4K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-VFQFN 裸露焊盘
包装: 带卷 (TR)
其它名称: ATMEGA645V-8MUR-ND
ATMEGA645V-8MURTR
23
2570N–AVR–05/11
ATmega325/3250/645/6450
Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.
When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at
the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has
been written to one by software, hardware clears the bit to zero after four clock cycles. See the
description of the EEWE bit for an EEPROM write procedure.
Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address
and data are correctly set up, the EEWE bit must be written to one to write the value into the
EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, oth-
erwise no EEPROM write takes place. The following procedure should be followed when writing
the EEPROM (the order of steps 3 and 4 is not essential):
1.
Wait until EEWE becomes zero.
2.
Wait until SPMEN in SPMCSR becomes zero.
3.
Write new EEPROM address to EEAR (optional).
4.
Write new EEPROM data to EEDR (optional).
5.
Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
6.
Within four clock cycles after setting EEMWE, write a logical one to EEWE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software
must check that the Flash programming is completed before initiating a new EEPROM write.
Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the
Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader
programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is
interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the
interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared
during all the steps to avoid these problems.
When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft-
ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set,
the CPU is halted for two cycles before the next instruction is executed.
Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct
address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the
EEPROM read. The EEPROM read access takes one instruction, and the requested data is
available immediately. When the EEPROM is read, the CPU is halted for four cycles before the
next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation is in
progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses. Table 8-1 lists the typical pro-
gramming time for EEPROM access from the CPU.
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