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| 型号： | ATMEGA645V-8MUR |
| 厂商： | Atmel |
| 文件页数： | 22/85页 |
| 文件大小： | 0K |
| 描述： | MCU AVR 64KB FLASH 8MHZ 64QFN |
| 产品培训模块： | megaAVR Introduction |
| 标准包装： | 4,000 |
| 系列： | AVR® ATmega |
| 核心处理器： | AVR |
| 芯体尺寸： | 8-位 |
| 速度： | 8MHz |
| 连通性： | SPI，UART/USART，USI |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 53 |
| 程序存储器容量： | 64KB（32K x 16） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 2K x 8 |
| RAM 容量： | 4K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.8 V ~ 5.5 V |
| 数据转换器： | A/D 8x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 64-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 其它名称： | ATMEGA645V-8MUR-ND ATMEGA645V-8MURTR |
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PIC16(L)F1824/1828
DS41419C-page 246
Preliminary
2010-2011 Microchip Technology Inc.
25.2
SPI Mode Overview
The Serial Peripheral Interface (SPI) bus is a
synchronous serial data communication bus that
operates in Full Duplex mode. Devices communicate in
a master/slave environment where the master device
initiates the communication. A slave device is
controlled through a chip select known as Slave Select.
The SPI bus specifies four signal connections:
Serial Clock (SCK)
Serial Data Out (SDO)
Serial Data In (SDI)
Slave Select (SS)
Figure 25-1 shows the block diagram of the MSSP1
module when operating in SPI Mode.
The SPI bus operates with a single master device and
one or more slave devices. When multiple slave
devices are used, an independent Slave Select con-
nection is required from the master device to each
slave device.
Figure 25-4 shows a typical connection between a
master device and multiple slave devices.
The master selects only one slave at a time. Most slave
devices have tri-state outputs so their output signal
appears disconnected from the bus when they are not
selected.
Transmissions involve two shift registers, eight bits in
size, one in the master and one in the slave. With either
the master or the slave device, data is always shifted
out one bit at a time, with the Most Significant bit (MSb)
shifted out first. At the same time, a new Least
Significant bit (LSb) is shifted into the same register.
Figure 25-5 shows a typical connection between two
processors configured as master and slave devices.
Data is shifted out of both shift registers on the pro-
grammed clock edge and latched on the opposite edge
of the clock.
The master device transmits information out on its SDO
output pin which is connected to, and received by, the
slave’s SDI input pin. The slave device transmits infor-
mation out on its SDO output pin, which is connected
to, and received by, the master’s SDI input pin.
To begin communication, the master device first sends
out the clock signal. Both the master and the slave
devices should be configured for the same clock polar-
ity.
The master device starts a transmission by sending out
the MSb from its shift register. The slave device reads
this bit from that same line and saves it into the LSb
position of its shift register.
During each SPI clock cycle, a full duplex data
transmission occurs. This means that while the master
device is sending out the MSb from its shift register (on
its SDO pin) and the slave device is reading this bit and
saving it as the LSb of its shift register, that the slave
device is also sending out the MSb from its shift register
(on its SDO pin) and the master device is reading this
bit and saving it as the LSb of its shift register.
After 8 bits have been shifted out, the master and slave
have exchanged register values.
If there is more data to exchange, the shift registers are
loaded with new data and the process repeats itself.
Whether the data is meaningful or not (dummy data),
depends on the application software. This leads to
three scenarios for data transmission:
Master sends useful data and slave sends dummy
data.
Master sends useful data and slave sends useful
data.
Master sends dummy data and slave sends useful
data.
Transmissions may involve any number of clock
cycles. When there is no more data to be transmitted,
the master stops sending the clock signal and it dese-
lects the slave.
Every slave device connected to the bus that has not
been selected through its slave select line must disre-
gard the clock and transmission signals and must not
transmit out any data of its own.
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| ATmega6490-16AI | 功能描述:8位微控制器 -MCU AVR 64K FLASH 2K EE 4K SRAM ADC LCD RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ATmega6490-16AU | 功能描述:8位微控制器 -MCU AVR 64K FLASH 2K EE 4K SRAM ADC LCD RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ATMEGA6490-16AUR | 功能描述:8位微控制器 -MCU AVR 64KB FLSH 2KB EE 4KB SRAM LCD16MHz,5V RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ATMEGA6490A-AU | 功能描述:8位微控制器 -MCU AVR 64KB FLSH 2KB EE 4KB SRAM-20MHz, IND RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ATMEGA6490A-AUR | 功能描述:8位微控制器 -MCU AVR 64KB FLSH 2KB EE 4KB SRAM-20MHz, IND RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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