参数资料
型号: ATTINY84A-SSU
厂商: Atmel
文件页数: 130/135页
文件大小: 0K
描述: IC MCU 8BIT 8K FLASH 14SOIC
标准包装: 55
系列: AVR® ATtiny
核心处理器: AVR
芯体尺寸: 8-位
速度: 20MHz
连通性: USI
外围设备: 欠压检测/复位,POR,PWM,温度传感器,WDT
输入/输出数: 12
程序存储器容量: 8KB(4K x 16)
程序存储器类型: 闪存
EEPROM 大小: 512 x 8
RAM 容量: 512 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
包装: 管件
94
32015G–AVR32–09/09
AT32AP7001
99. The oscillator has a rather long start-up time of 32768 clock cycles, and no clocks will be
generated in the device during this start-up time.
Note that in static sleep mode the startup counter will start at the negedge of reset and not at the
posedge.
Pulling OSCEN_N high will also disable the 32 KHz oscillator, and a 32 KHz clock must be
applied on the XIN32 pin. No start-up time applies to this clock.
11.5.3
PLL operation
The device contains two PLL’s, PLL0 and PLL1. These are disabled by default, but can be
enabled to provide high frequency source clocks for synchronous or generic clocks. The PLL’s
can take either Oscillator 0 or 1 as clock source. Each PLL has an input divider, which divides
the source clock, creating the reference clock for the PLL. The PLL output is divided by a user-
defined factor, and the PLL compares the resulting clock to the reference clock. The PLL will
adjust its output frequency until the two compared clocks are equal, thus locking the output fre-
quency to a multiple of the reference clock frequency.
When the PLL is switched on, or when changing the clock source or multiplication or division
factor for the PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for
the digital logic is automatically masked when the PLL is unlocked, to prevent connected digital
logic from receiving a too high frequency and thus become unstable.
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