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| 型号： | AXDA2600DKV3D |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2083 MHz, MICROPROCESSOR, CPGA453 |
| 封装： | OPGA-453 |
| 文件页数： | 55/106页 |
| 文件大小： | 2275K |
| 代理商： | AXDA2600DKV3D |
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40
Electrical Data
Chapter 8
AMD Athlon XP Processor Model 8 Data Sheet
25175H—March 2003
Preliminary Information
TBIT
Input Time to Acquire
20.0
ns
7, 8
TRPT
Input Time to Reacquire
40.0
ns
9–13
TRISE
Signal Rise Time
1.0
3.0
V/ns
6
TFALL
Signal Fall Time
1.0
3.0
V/ns
6
CPIN
Pin Capacitance
4
12
pF
TVALID
Time to data valid
100
ns
14
Table 16. General AC and DC Characteristics (continued)
Symbol
Parameter Description
Condition
Min
Max
Units
Notes
Notes:
1. Characterized across DC supply voltage range.
2. Values specified at nominal VCC_CORE . Scale parameters between VCC_CORE. minimum and VCC_CORE. maximum.
3. IOL and IOH are measured at VOL maximum and VOH minimum, respectively.
4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
5. These are aggregate numbers.
6. Edge rates indicate the range over which inputs were characterized.
7. In asynchronous operation, the signal must persist for this time to enable capture.
8. This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST.
9. The approximate value for standard case in normal mode operation.
10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.
11. Reassertions of the signal within this time are not guaranteed to be seen by the core.
12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other
configurations.
14. Time to valid is for any open-drain pins. See requirements 7 and 8 in the “Power-Up Timing Requirements“ chapter for more
information.
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相关代理商/技术参数 |
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| AXDA2800DKV4D | 制造商:Advanced Micro Devices 功能描述:MPU AMD Athlon XP 64-Bit 0.13um 2.083GHz 453-Pin OPGA |
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