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参数资料
| 型号： | B900J24FXX12IT |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 59.88 MHz, OTHER DSP, PQFP44 |
| 文件页数： | 11/100页 |
| 文件大小： | 1547K |
| 代理商： | B900J24FXX12IT |
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18
Lucent Technologies Inc.
B900
Advance Data Sheet
Baseband Signal Processor
July 1999
4 Hardware Architecture (continued)
4.1
B900 Architectural Overview (continued)
4.1.1 DSP1600 Core
The DSP1600 core is the heart of the B900 device.
The core consists of a data arithmetic unit (DAU), two
address arithmetic units (XAAU and YAAU), an instruc-
tion cache, and a control section. The core provides
support for internal dual-port RAM and features vec-
tored interrupts and a trap mechanism. (For more infor-
mation, see Section 4.2 on page 20.)
4.1.2 Dual-Port RAM (DPRAM)
This module contains two banks of zero wait-state
memory in the B900. It consists of 2K 16-bit words and
has separate address and data ports to the instruction/
coefficient and data memory spaces. A program can
reference memory from either space at any time, trans-
parently and without restriction. The DSP1600 core
automatically performs the required multiplexing. In the
event that references to both ports of a single bank of
DPRAM are made simultaneously, the DSP1600 core
automatically inserts a wait-state and performs the
data-port access first, followed by the instruction/coeffi-
cient-port access.
A program can be downloaded from slow external
memory into DPRAM and then be executed without
wait-states. DPRAM is also useful for improving convo-
lution performance in cases where the coefficients are
adaptive. Because DPRAM can be downloaded
through the JTAG port, full-speed, remote in-circuit
emulation is possible. DPRAM can also be used for
downloading self-test code through the JTAG port.
4.1.3 Read-Only Memory (ROM)
The B900 contains 24K of 16-bit words of conventional
ROM for program and fixed coefficients. A mask-
programmable secure option is available on production
chips. This option prohibits reading out the ROM con-
tents externally. This is accomplished by prohibiting the
selection of memory map 3.
4.1.4 Timers
Two interrupt timers are provided in the B900. They are
used to provide an interrupt at the expiration of a pro-
grammed interval. The interrupt may be a single inter-
rupt or a repetitive interrupt. TIMER0 runs on either the
free-running core clock (CLKFREE) or low-frequency
clock (CLKLOW), has a clock prescaler, and supports
over nine orders of magnitude of interval selection.
TIMER1 runs on either the free-running core clock
(CLKFREE) or low-frequency clock (CLKLOW), has a
prescaler, and supports over nine orders of magnitude
of interval selection. The timers may be stopped and
restarted at any time. For more information, see Sec-
4.1.5 Watchdog Timer
A watchdog timer can be used to protect from cata-
strophic loss of control of the B900. It can be pro-
grammed for one of three time-out intervals. The
watchdog timer clock is selectable as the divided-down
(divide by 128 only) input clock or the internal ring
oscillator output. For more information, see Section
4.9.
4.1.6 Input/Output Ports (IOP)
Three 8-bit IOP units (IOPA, IOPB, IOPC) and one
4-bit IOP unit (IOPD) for the 44-pin devices provide
convenient and efficient monitoring and control of 28
individually configurable pins. The 28-pin DSP1609
has only two IOP units (IOPB and IOPC). When config-
ured as outputs, the pins can be individually set,
cleared, toggled, or left unchanged. When configured
as inputs, the entire port can be read (those configured
as inputs or multiplexed, as well as those configured as
outputs). Note that some of the pins of the IOP units
are multiplexed with other functions. See Section 4.7.
4.1.7 JTAG
The JTAG section contains logic that implements the
JTAG/
IEEE* P1149.1 standard four-signal test port.
No boundary-scan register is included. The JTAG port
provides a mechanism for the DSP1600 core to com-
municate with remote test equipment or a remote
hardware development system (
FlashDSP 1600HDS).
The JTAG port also supports program, memory, and
register upload/download, and execution start/stop.
A 4-bit instruction register, a bypass register, and a
device identification register have been implemented
(see Table 45 on page 56). The instructions for access-
ing the ID and BYPASS registers are 0xE (1110) and
0xF (1111), respectively. There is no separate TRST
input pin.
*
IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
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| B-900-M-10-EG | 制造商:Thomas & Betts 功能描述: |
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