- 您现在的位置：买卖IC网 > PDF目录166397 > B900J24FXX12IT 0-BIT, 59.88 MHz, OTHER DSP, PQFP44 PDF资料下载
参数资料
| 型号： | B900J24FXX12IT |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 59.88 MHz, OTHER DSP, PQFP44 |
| 文件页数： | 17/100页 |
| 文件大小： | 1547K |
| 代理商： | B900J24FXX12IT |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页当前第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页
Lucent Technologies Inc.
23
Advance Data Sheet
B900
July 1999
Baseband Signal Processor
4 Hardware Architecture (continued)
4.3
Interrupts, Trap, and Low-Power
Standby Mode (continued)
4.3.1 Interruptibility
Vectored interrupts are serviced only after an interrupt-
ible instruction or the completion of a prior interrupt
service routine. If more than one vectored interrupt is
asserted at the same time, the interrupts are serviced
sequentially according to their assigned priorities.
Interrupt service routines, branch and conditional
branch instructions, cache loops, and instructions that
only decrement one of the RAM pointers,
r0 to r3 (e.g., *r3– –), are not interruptible.
A trap is similar to an interrupt, but it gains control of
the processor by branching to the trap service routine
even when the current instruction is noninterruptible. It
may not be possible to return to normal instruction exe-
cution from the trap service routine because the
machine state cannot always be saved. In particular,
program execution cannot be continued from a trapped
cache loop or interrupt service routine. While in a trap
service routine, another trap is ignored.
When set to 1, the status bits in the ins register indi-
cate that an interrupt has occurred. The processor
must reach an interruptible state (completion on an
interruptible instruction or a prior interrupt service rou-
tine) before an enabled vectored interrupt can be acted
on. An interrupt cannot be serviced if it is not enabled.
Polled interrupt service can be implemented by dis-
abling the interrupt in the inc register and polling the
ins register for the expected event.
4.3.2 Vectored Interrupts
A logic 1 written to any bit of the inc enables (or
unmasks) the associated interrupt. If the bit is cleared
to a logic 0, the interrupt is disabled (or masked). The
occurrence of an interrupt that is not masked causes
the program execution to transfer to the memory loca-
tion pointed to by that interrupt’s vector address,
assuming no other interrupt is being serviced.
The occurrence on an interrupt that is masked causes
no automatic processor action, but it does set the cor-
responding status bit in the ins register. If an interrupt
occurs while it is masked, it is latched. Subsequently,
unmasking the interrupt causes it to be serviced as
soon as the processor reaches an interruptible state.
The status of the interrupt sources is readable in the
ins register even if the interrupt is masked in the inc
register.
4.3.3 External Interrupt Pin (INTB)
INTB is a negative edge-triggered interrupt pin. Exter-
nal hardware must guarantee that the interrupt service
routine has completed before issuing another interrupt
on INTB. Any activity on INTB is not recognized during
the interrupt service routine and must be reissued after
the completion of the interrupt service routine. Be-
cause there is no interrupt acknowledge pin on the
B900, the interrupt service routine must communicate
with the external hardware through other means. One
possible way of performing this task would be through
the use of IOP pins.
Table 11. Interrupt Vectors
Source
Vector Priority
Issued By
No interrupt
0x0
—
Software
interrupt
0x2
1
(lowest)
icall
SW3
0x1
2
—
JINT
0x42
3
JTAG interrupt
TIME0
0x4
4
TIMER0
SW4
0x8
5
—
IOPA
0xc
6
IOPA interrupt
IBFB
0x10
7
SIO (channel B)
input buffer full
INTB
0x14
8
INTB pin
SW5
0x18
9
—
No interrupt
0x1c
—
SSI
0x20
10
SSI
SW6
0x24
11
—
SW7
0x28
12
—
IBF
0x2c
13
SIO (channel A)
input buffer full
SW1
0x30
14
—
TIME1
0x34
15
TIMER1
SW2
0x38
16
—
Trap from JTAG
0x3
17
JTAG/HDS
相关PDF资料 |
PDF描述 |
|---|---|
| BA00CC0WCP-V5 | 1A Low Dropout Voltage Regulator with Shut Down Switch(Adustable Voltage) |
| BA10E6 | COPPER ALLOY, TIN FINISH, RING TERMINAL |
| BA12004 | 0.5 A, 7 CHANNEL, NPN, Si, POWER TRANSISTOR |
| BA1518SUR5VP | SINGLE COLOR DISPLAY CLUSTER, ULTRA RED |
| BA1524LUR5VP | SINGLE COLOR DISPLAY CLUSTER, ULTRA RED |
相关代理商/技术参数 |
参数描述 |
|---|---|
| B-900-M-10 | 制造商:Thomas & Betts 功能描述: |
| B-900-M-10-EG | 制造商:Thomas & Betts 功能描述: |
| B-900-M-20 | 制造商:Thomas & Betts 功能描述: |
| B-900-M-20-EG | 制造商:Thomas & Betts 功能描述: |
| B901 | 制造商:EDAL 制造商全称:EDAL 功能描述:Silicon Bridge Rectifier |
发布紧急采购，3分钟左右您将得到回复。