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参数资料
| 型号： | B900J24FXX12IT |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 59.88 MHz, OTHER DSP, PQFP44 |
| 文件页数： | 18/100页 |
| 文件大小： | 1547K |
| 代理商： | B900J24FXX12IT |
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24
Lucent Technologies Inc.
B900
Advance Data Sheet
Baseband Signal Processor
July 1999
4 Hardware Architecture (continued)
4.3
Interrupts, Trap, and Low-Power
Standby Mode (continued)
4.3.4 Clearing Interrupts
The IOPA interrupt is cleared by reading the sbita reg-
ister. The JTAG interrupt (JINT) is cleared by reading
the jtag register.
Other interrupts are cleared by either of the following
methods:
s
After a vectored interrupt has been serviced, it is
cleared when the ireturn instruction is issued,
leaving set any other vectored interrupts that are
pending.
s
In the ins register, writing a 1 to the bit that is associ-
ated with the interrupt. Writing a 0 to the ins register
does nothing.
Once an interrupt is cleared, the corresponding bit in
the ins register is cleared.
4.3.5 Power-Saving Modes
Three primary power-saving modes are available.
These modes are described below in order of increas-
ing power savings:
Low-Frequency Clock Mode—Switching the core
clock to the lowest frequency possible for as long as
possible is the easiest way to conserve power, since
power consumption is directly linked to the instruction
cycle rate. The low-frequency clock source to the B900
is controlled by register bits clkc[7:4]. The appropriate
selection of the low-frequency clock depends on the
application requirements. If an application requires an
accurate real-time clock, the internal ring oscillator
cannot be used.
Low-Power Standby Mode—Setting the AWAIT bit in
the alf register causes the processor to go into a
standby mode in which program execution is halted
and the internal wait-stated B900 clock is turned off.
The occurrence of any interrupt that is enabled in the
inc register is processed and returns the processor to
the previous state, allowing program execution to con-
tinue.
Stop-Clock Mode—Setting the STOPCLK bit in the
clkc register causes the processor to go into a sleep
mode in which program execution is halted and the
clock to the B900 core is turned off. An IOPA interrupt,
an INTB pin interrupt, or a TIMER0 or TIMER1 time-
out interrupt, when running off of the low-frequency
clock, clears the STOPCLK condition and allows pro-
gram execution to continue. (The desired pin interrupts
must be selected with the appropriate multiplexing con-
trols in order to use these interrupts for exiting stop-
clock mode.) The settings of the inc register have no
effect on the clearing of STOPCLK.
4.4
Memory Maps and Wait-States
The B900 implements a modified Harvard architecture
that has separate internal 16-bit address and data
buses for the instruction/coefficient (X) and data (Y)
memory spaces. The B900 contains 24 Kwords of
flash ROM and two banks of 2 Kwords of RAM.
The instruction/coefficient memory map is configurable
to provide application flexibility.
Table 12 shows the instruction/coefficient memory
maps available for the B900.
The data memory maps are divided into segments as
shown in Table 13. The selection of a segment is auto-
matic depending on the address in the YAAU.
The internal RAM can be accessed by both the Y
space and the X space. If the same bank of internal
RAM is accessed from both memory spaces simulta-
neously, one wait-state is added, and the Y space is
accessed first.
4.4.1 Instruction/Coefficient Memory Map Selection
In determining which memory map to use, the proces-
sor evaluates the state of the LOWPR bit (bit 14) of the
alf register. The LOWPR bit of the alf register is initial-
ized to 0 automatically at reset. LOWPR controls the
address in memory assigned to the two 1K banks of
dual-port RAM (i.e., RAM1 and RAM2). If LOWPR is
low, internal dual-port RAM begins at address 0xC000.
If LOWPR is high, internal dual-port RAM begins at
address 0x0. LOWPR also moves IROM from 0x0 in
MAP1 to 0x4000 in MAP3.
The Lucent development system tools using the JTAG
port can independently set the memory map. Specifi-
cally, during a trap from JTAG, the memory map is
forced to MAP1. The map selection made prior to the
JTAG trap is restored when the trap service routine has
completed execution.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| B-900-M-10 | 制造商:Thomas & Betts 功能描述: |
| B-900-M-10-EG | 制造商:Thomas & Betts 功能描述: |
| B-900-M-20 | 制造商:Thomas & Betts 功能描述: |
| B-900-M-20-EG | 制造商:Thomas & Betts 功能描述: |
| B901 | 制造商:EDAL 制造商全称:EDAL 功能描述:Silicon Bridge Rectifier |
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