参数资料
型号: BD00C0AWFP-E2
厂商: Rohm Semiconductor
文件页数: 12/21页
文件大小: 0K
描述: IC REG LDO ADJ 1A TO252-5
标准包装: 2,000
稳压器拓扑结构: 正,可调式
输出电压: 3 V ~ 15 V
输入电压: 4 V ~ 25 V
电压 - 压降(标准): 0.3V @ 500mA
稳压器数量: 1
电流 - 输出: 1A(最小值)
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: TO-252-5,DPak(4 引线 + 接片),TO-252AD
供应商设备封装: *
包装: 带卷 (TR)
BD00C0AWxx series
Datasheet
● Operational Notes
1. Absolute maximum ratings
Exceeding the absolute maximum rating for supply voltage, operating temperature or other parameters can result in
damages to or destruction of the chip. In this event it also becomes impossible to determine the cause of the damage
(e.g. short circuit, open circuit, etc). Therefore, if any special mode is being considered with values expected to exceed
the absolute maximum ratings, implementing physical safety measures, such as adding fuses, should be considered.
2. The electrical characteristics given in this specification may be influenced by conditions such as temperature, supply
voltage and external components. Transient characteristics should be sufficiently verified..
3. GND electric potential
Keep the GND pin potential at the lowest (minimum) level under any operating condition. Furthermore, ensure that,
including the transient, none of the pin’s voltages are less than the GND pin voltage.
4. Ground wiring pattern
When both a small-signal GND and a high current GND are present, single-point grounding (at the set standard point) is
recommended. This in order to separate the small-signal and high current patterns and to ensure that voltage changes
stemming from the wiring resistance and high current do not cause any voltage change in the small-signal GND. Similarly,
care must be taken to avoid wiring pattern fluctuations in any connected external component GND.
5. Inter-pin shorting and mounting errors
Ensure that when mounting the IC on the PCB the direction and position are correct. Incorrect mounting may result in
damaging the IC. Also, shorts caused by dust entering between the output, input and GND pin may result in damaging
the IC.
6. Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
7. Inspection using the set board
The IC needs to be discharged after each inspection process as, while using the set board for inspection, connecting a
capacitor to a low-impedance pin may cause stress to the IC. As a protection from static electricity, ensure that the
assembly setup is grounded and take sufficient caution with transportation and storage. Also, make sure to turn off the
power supply when connecting and disconnecting the inspection equipment.
8. Power dissipation (Pd)
Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in
deterioration of the properties of the chip. The absolute maximum rating of the Pd stated in this specification is when the
IC is mounted on a 70mm×70mm×1.6mm glass epoxy board. In case of exceeding this absolute maximum rating,
increase the board size and copper area to prevent exceeding the Pd rating.
9. Thermal design
The power dissipation under actual operating conditions should be taken into consideration and a sufficient margin
should be allowed for in the thermal design. On the reverse side of the package this product has an exposed heat pad for
improving the heat dissipation. Use both the front and reverse side of the PCB to increase the heat dissipation pattern as
far as possible. The amount of heat generated depends on the voltage difference across the input and output, load
current, and bias current. Therefore, when actually using the chip, ensure that the generated heat does not exceed the
Pd rating.
Tjmax: Maximum junction temperature=150[ ℃ ], Ta: Peripheral temperature [ ℃ ],
θ ja : Thermal resistance of package-ambience[ ℃ /W], Pd : Package Power dissipation [W],
Pc: Power dissipation [W], V CC : Input Voltage, V O : Output Voltage, I O : Load, Ib : Circuit Current
Package Power dissipation
Power dissipation
: Pd (W) = (Tjmax-Ta) / θ ja
: Pc (W) = (V CC -V O ) × I O +V CC × Ib
10. V CC pin
Insert a capacitor(V O ≥ 5.0V:capacitor ≥ 1μF, 3.0 ≤ V O < 5.0V:capacitor ≥ 2.2μF) between the V CC and GND pins. Choose the
capacitance according to the line between the power smoothing circuit and the V CC pin. Selection of the capacitance also
depends on the application. Verify the application and allow for sufficient margins in the design. We recommend using a
capacitor with excellent voltage and temperature characteristics.
Electric capacitance
IC
Ceramic capacitors, Low ESR capacitor
www.rohm.com
? 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
12/18
TSZ02201-0T2T0AZ00060-1-2
08.Feb.2013 Rev.001
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