参数资料
| 型号： | BD00D0AWHFP-TR |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ 2A HRP5 |
| 标准包装： | 2,000 |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 3 V ~ 15 V |
| 输入电压： | 4 V ~ 25 V |
| 电压 - 压降（标准）： | 0.4V @ 1A |
| 稳压器数量： | 1 |
| 电流 - 输出： | 2A（最小值） |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | HRP-5 |
| 供应商设备封装： | HRP-5 |
| 包装： | 带卷 (TR) |
BD00D0AWHFP
Technical Note
● Notes for use
1. Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings (such as the input voltage or operating temperature range) may
result in damage to the IC. Assumptions should not be made regarding the state of the IC (e.g., short mode or open mode)
when such damage is suffered. If operational values are expected to exceed the maximum ratings for the device, consider
adding protective circuitry (such as fuses) to eliminate the risk of damaging the IC.
2. Electrical characteristics described in these specifications may vary, depending on temperature, supply voltage, external
circuits and other conditions. Therefore, be sure to check all relevant factors, including transient characteristics.
3. GND potential
The potential of the GND pin must be the minimum potential in the system in all operating conditions.
Ensure that no pins are at a voltage below the GND at any time, regardless of transient characteristics.
4. Ground wiring pattern
When using both small-signal and large-current GND traces, the two ground traces should be routed separately but
connected to a single ground potential within the application in order to avoid variations in the small-signal ground caused
by large currents. Also ensure that the GND traces of external components do not cause variations on GND voltage.
The power supply and ground lines must be as short and thick as possible to reduce line impedance.
5. Inter-pin shorts and mounting errors
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in
damage to the IC. Shorts between output pins or between output pins and the power supply or GND pins (caused by poor
soldering or foreign objects) may result in damage to the IC.
6. Operation in strong electromagnetic fields
Using this product in strong electromagnetic fields may cause IC malfunction. Caution should be exercised in applications
where strong electromagnetic fields may be present.
7. Testing on application boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance pin may subject the IC to
stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always be
turned off completely before connecting or removing it from a jig or fixture during the evaluation process. To prevent
damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage.
8. Thermal consideration
Use a thermal design that allows for a sufficient margin in light of the Pd in actual operating conditions.
Consider Pc that does not exceed Pd in actual operating conditions. (Pd ≧ Pc)
Tjmax : Maximum junction temperature=150[ ℃ ] , Ta : Peripheral temperature[ ℃ ] ,
θ ja : Thermal resistance of package-ambience[ ℃ /W], Pd : Package Power dissipation [W],
Pc : Power dissipation [W], Vcc : Input Voltage, Vo : Output Voltage, Io : Load, Ib : Bias Current
Package Power dissipation
Power dissipation
: Pd (W)=(Tjmax － Ta)/ θ ja
: Pc (W)=(Vcc － Vo) × Io+Vcc × Ib
9. Vcc pin
Insert a capacitor(Vo ≧ 5V:capacitor ≧ 1μF ～ , Vo ＜ 5V:capacitor ≧ 2.2μF ～ ) between the Vcc and GND pins.
The appropriate capacitance value varies by application. Be sure to allow a sufficient margin for input voltage levels.
Electric capacitance
IC
Ceramic capacitors, Low ESR capacitors
www.rohm.com
? 2011 ROHM Co., Ltd. All rights reserved.
8/11
2011.03 - Rev.A
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