参数资料
型号: BD9140MUV-E2
厂商: Rohm Semiconductor
文件页数: 11/21页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 2A VQFN020
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 2.5 V ~ 6 V
输入电压: 4.5 V ~ 13.2 V
PWM 型: 电流模式
频率 - 开关: 500kHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 20-VFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: VQFN020V4040
BD9141MUV
● Switching Regulator Efficiency
Efficiency ? may be expressed by the equation shown below:
Datasheet
η =
V OUT × I OU T
Vin × Iin
× 100[%]=
P OUT
Pin
× 100[%]=
P OUT
P OUT +P D α
× 100[%]
1) ON resistance dissipation of inductor and FET : PD(I R)
1)PD(I R)=I OUT × (R COIL +R ON ) (R COIL [ Ω ] : DC resistance of inductor, R ON [ Ω ] : ON resistance of FET, I OUT [A] : Output
2)PD(Gate)=Cgs × f × V
(Cgs[F] : Gate capacitance of FET, f[H] : Switching frequency, V[V] : Gate driving voltage of FET)
Vin × C RSS × I OUT × f
I DRIVE
4)PD(ESR)=I RMS × ESR (I RMS [A] : Ripple current of capacitor, ESR[ Ω ] : Equivalent series resistance.)
Efficiency may be improved by reducing the switching regulator power dissipation factors P D α as follows:
Dissipation factors:
2
2) Gate charge/discharge dissipation : PD(Gate)
3) Switching dissipation : PD(SW)
4) ESR dissipation of capacitor : PD(ESR)
5) Operating current dissipation of IC : PD(IC)
2 2
current.)
2
2
3)PD(SW)= (C RSS [F] : Reverse transfer capacitance of FET, I DRIVE [A] : Peak current of gate.)
2
5)PD(IC)=Vin × I CC (I CC [A] : Circuit current.)
● Consideration on Permissible Dissipation and Heat Generation
As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is
needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input
voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation
must be carefully considered.
For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered.
Because the conduction losses are considered to play the leading role among other dissipation mentioned above including
gate charge/discharge dissipation and switching dissipation.
4 layers (Copper foil area : 5505mm )
P=I OUT × R ON
4.0
3.0
2.0
1.0
① 3.56W
② 2.21W
③ 0.70W
2
copper foil in each layers.
θ j-a=35.1 ℃ /W
② 4 layers (Copper foil area : 10.29m 2 )
copper foil in each layers.
θ j-a=56.6 ℃ /W
③ 4 layers (Copper foil area : 10.29m 2 )
θ j-a=178.6 ℃ /W
④ IC only.
θ j-a=367.6 ℃ /W
2
R ON =D × R ONP +(1-D)R ONN
D : ON duty (=V OUT /V CC )
R COIL : DC resistance of coil
R ONP : ON resistance of P-channel MOS FET
R ONN : ON resistance of N-channel MOS FET
I OUT : Output current
④ 0.34W
0
0
25
50
75
100 105 125
150
P=2 × 0.12375 = 0.495[W]
Ambient temperature:Ta [ ℃ ]
Fig.27 Thermal derating curve
(VQFN020V4040)
If V CC =8V, V OUT =5V, R ONP =0.15 Ω , R ONN =0.08 Ω
I OUT =2A, for example,
D=V OUT /V CC =5/8=0.625
R ON =0.625 × 0.15+(1-0.625) × 0.08
=0.09375+0.03
=0.12375[ Ω ]
2
As R ONP is greater than R ONN in this IC, the dissipation increases as the ON duty becomes greater.
consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed.
With the
www.rohm.com
?2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
11/19
TSZ02201-0J3J0AJ00180-1-2
02.MAR.2012 Rev.001
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