参数资料
| 型号： | BD9300F-E2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 14/17页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST INV PWM 14-SOP |
| 标准包装： | 1 |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 800kHz |
| 占空比： | 100% |
| 电源电压： | 3.6 V ~ 35 V |
| 降压： | 是 |
| 升压： | 是 |
| 回扫： | 无 |
| 反相： | 是 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 14-SOIC（0.173"，4.40mm 宽） |
| 包装： | 标准包装 |
| 产品目录页面： | 1373 (CN2011-ZH PDF) |
| 其它名称： | BD9300F-E2DKR |
Cautions on use
1) Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the
devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to
exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses.
2) GND potential
Ground-GND potential should maintain at the minimum ground voltage level. Furthermore, no terminals should be lower than the GND
potential voltage including an electric transients.
3) Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
4) Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or if
positive and ground power supply terminals are reversed. The IC may also be damaged if pins are shorted together or are shorted to other
circuitís power lines.
5) Operation in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.
6) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always
discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to, or removing it from a jig or
fixture, during the inspection process. Ground the IC during assembly steps as an antistatic measure. Use similar precaution when
transporting and storing the IC.
7) IC pin input
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements to keep them isolated. P?N junctions are
formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode or transistor. For example, the
relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P?N junction operates as a parasitic diode.
When Pin B > GND > Pin A, the P?N junction operates as a parasitic transisto r.
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among
circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is
lower than the GND (P substrate) voltage to an input pin, should not be used.
(Pin A)
Resistor
(Pin B)
Transistor (NPN)
B
C
E
N
GND
P+
P
P+
P+
P
P+
N
N
N
Player
Parasitic element
GND
N
N
Parasitic element
P laye r
GND
N
(Pin B)
(Pin A)
GND
Parasitic element
Fig. 28 Typical simple construction of monolithic IC
B
C
E
GND
Parasitic element
8) Ground wiring pattern
The power supply and ground lines must be as short and thick as possible to reduce line impedance. Fluctuating voltage
on the power ground line may damage the device.
14/16
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