参数资料
型号: BR24L32FJ-WE2
厂商: Rohm Semiconductor
文件页数: 36/41页
文件大小: 0K
描述: IC EEPROM 32KBIT 400KHZ 8SOP
标准包装: 1
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 32K (4K x 8)
速度: 400kHz
接口: I²C,2 线串口
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOP-J
包装: 标准包装
产品目录页面: 1379 (CN2011-ZH PDF)
其它名称: BR24L32FJ-WE2DKR
BR24L □□ -W Series,BR24S □□□ -W Series
Technical Note
● I 2 C BUS input / output circuit
○ Input (A0, A1, A2, SCL, WP)
Fig.54 Input pin circuit diagram
○ Input/Output (SDA)
Fig.55 Input /output pin circuit diagram
● Notes on power ON
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action,
observe the following condition at power on.
1. Set SDA = 'H' and SCL ='L' or 'H'
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
V CC
tR
Recommended conditions of tR,tOFF,Vbot
tR
tOFF
Vbot
0
tOFF
Vbot
10ms or below
100ms or below
10ms or longer
10ms or longer
0.3V or below
0.2V or below
Fig.56 Rise waveform diagram
3. Set SDA and SCL so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above conditions 1 cannot be observed. When SDA becomes 'L' at power on .
→ Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
V CC
tLOW
SCL
SDA
After Vcc becomes stable
After Vcc becomes stable
tDH
tSU:DAT
tSU:DAT
Fig.57 When SCL='H' and SDA='L'
Fig.58 When SCL='H' and SDA='L'
b) In the case when the above condition 2 cannot be observed.
→ After power source becomes stable, execute software reset(P26).
c) In the case when the above conditions 1 and 2 cannot be observed.
→ Carry out a), and then carry out b).
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? 2009 ROHM Co., Ltd. All rights reserved.
36/40
2009.09 - Rev.D
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