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参数资料
| 型号： | BR25L010F-WE2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 11/17页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM SER 1KB SPI BUS 8SOIC |
| 标准包装： | 3,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 1K (128 x 8) |
| 速度： | 5MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 带卷 (TR) |
BR25L010-W, BR25L020-W, BR25L040-W, BR25L080-W, BR25L160-W, BR25L320-W, BR25L640-W
Method to cancel each command
Technical Note
READ
Method to cancel : cancel by CS = "H"
Ope code
8 bits
Address
8 bits /16bits
Data
8 bits
Cancel available in all areas of read mode
Fig.48 READ cancel valid timing
RDSR
Method to cancel : cancel by CS = "H"
Ope code
8 bits
Data
8 bits
Cancel available in all
areas of read mode
Fig.49 RDSR cancel valid timing
WRITE, PAGE WRITE
a : Ope code, address input area.
Cancellation is available by CS = "H".
b : Data input area (D7 ~ D1 input area)
Ope code
8 bits
Address
8 bits
a
Data (n)
8 bits
b
tE/W
d
Cancellation is available by CS = "H".
c : Data input area (D0 area)
When CS is started, write starts.
After CS rise, cancellation cannot be made by any
means.
d : tE/W area
Cancellation is available by CS = "H". However, when
SCK
Fig.50 WRITE cancel valid timing
c
write starts (CS is started) in the area c, cancellation
SI
D7
D6
D5
D4
D3
D2
D1
D0
cannot be made by any means. And, by inputting on
b
c
SCK clock, cancellation cannot be made. In page write
mode, there is write enable area at every 8 clocks.
Note 1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once
again.
Note 2) If CS is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable,
therefore, it is necessary to fall in SCK = "L" area. As for SCK rise, assure timing of tCSS / tCSH or higher.
WRSR
SCK
14
15
16
17
a : From ope code to 15 clock rise
Cancel by CS = "H".
SI
D1
D0
b : From 15 clock rise to 16 clock rise (write enable area)
a
b
c
When CS is started, write starts.
After CS rise, cancellation cannot be made by any
Ope code
Address
tE/W
means.
c : After 16 clock rise
8 bit
a
8 bit
c
Cancel by CS = "H". However, when write starts (CS is
started) in the area b, cancellation cannot be made by
b
Fig.51 WRSR cancel valid timing
any means. And, by inputting on SCK clock, cancellation
cannot be made.
Note 1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once
again.
Note 2) If CS is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable,
therefore, it is necessary to fall in SCK = "L" area. As for SCK rise, assure timing of tCSS/tCSH or higher.
WREN/WRDI
a : From ope code to clock rise, cancel by CS = "H".
b : Cancellation is not available when CS is started after 7 clock.
SCK
7
a
8
b
9
Ope code
8 bit
a
b
Fig.52 WREN / WRDI cancel valid timing
www.rohm.com
? 2010 ROHM Co., Ltd. All rights reserved.
11/16
2010.07 - Rev. B
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相关代理商/技术参数 |
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|---|---|
| BR25L010-W | 制造商:ROHM 制造商全称:Rohm 功能描述:SPI BUS Serial EEPROMs |
| BR25L010-W_08 | 制造商:ROHM 制造商全称:Rohm 功能描述:SPI BUS Serial EEPROMs |
| BR25L010-W_10 | 制造商:ROHM 制造商全称:Rohm 功能描述:SPI BUS Serial EEPROMs |
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| BR25L020FJ-WE2 | 功能描述:电可擦除可编程只读存储器 SPI 256X8 BIT RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
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