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参数资料
| 型号： | BR25S256F-WE2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 14/19页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM SPI 256KB 20MHZ 8-SOP |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 256K (32K x 8) |
| 速度： | 20MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 1.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-SOP |
| 包装： | 标准包装 |
| 其它名称： | BR25S256F-WE2DKR |
BR25S □□□ Series
Technical Note
● Notes on power ON/OFF
At standby
Set CSB “H”, and be sure to set SCK, SI input “L” or “H”. Do not input intermediate electric potantial.
At power ON/OFF
When Vcc rise or fall, set CSB=”H” (=Vcc).
When CSB is “L”, this IC gets in input accept status (active). If power is turned on in this status, noises and the likes may
cause malfunction, erroneous write or so. To prevent these, at power ON, set CSB “H”. (When CSB is in “H” status, all
inputs are canceled.)
Vcc
CSB
Good example
Bad example
Fig.54 CSB timing at power ON/OFF
(Good example) CSB terminal is pulled up to Vcc.
At power OFF, take 10ms or more before supply. If power is turned on without observing this condition, the IC
internal circuit may not be reset.
(Bad example)
CSB terminal is “L” at power ON/OFF.
In this case, CSB always becomes “L” (active status), and EEPROM may have malfunction or erroneous write owing
to noises and the likes.
Even when CSB input is High-Z, the status becomes like this case.
○ Operating timing after power ON
As shown in Fig.55, at standby, when SCK is “H”, even if CSB is fallen, SI status is not read at fall edge. SI status is read
at SCK rise edge after fall of CSB. At standby and at power ON/OFF, set CSB “H” status.
Even if CSB is fallen at SCK=”H”,
SI status is not read at that edge.
CSB
Command start here. SI is read.
SCK
0
1
2
SI
Fig.55
Operating timing
At power on malfunction preventing function
This IC has a POR (Power On Reset) circuit as mistake write countermeasure. After POR action, it gets in write disable
status. The POR circuit is valid only when power is ON, and does not work when power is OFF. When power is ON, if the
recommended conditions of the following tR, tOFF, and Vbot are not satisfied, it may become write enable status owing to
noises and the likes.
Vcc
tR
Recommended conditions of t R , t OFF , Vbot
t R
t OFF
V bot
0
tOFF
Vbot
10ms or below
100ms or below
10ms or higher
10ms or higher
0.3V or below
0.2V or below
Fig.56 Rise waveform
○ Low voltage malfunction preventing function
LVCC (Vcc-Lockout) circuit prevents data rewrite action at low power, and prevents wrong write.
At LVCC voltage (Typ. =1.2V) or below, it prevent data rewrite.
www.rohm.com
? 2010 ROHM Co., Ltd. All rights reserved.
14/18
2010.12 - Rev.B
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