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参数资料
| 型号： | BU-62743B3-102 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128 |
| 封装： | 0.815 X 0.815 INCH, 0.140 INCH HEIGHT, 1 MM PITCH, BGA-128 |
| 文件页数： | 78/93页 |
| 文件大小： | 504K |
| 代理商： | BU-62743B3-102 |
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Data Device Corporation
62743_pre2.DOC
www.ddc-web.com
8-15-01
8
Table 1. PCI Enhanced Mini-ACE Specifications
PARAMETER
MIN
TYP
MAX
UNITS
Notes:
Notes 1 through 6 are applicable to the Receiver Differential Resistance and
Differential Capacitance specifications:
(1)
Specifications include both transmitter and receiver (tied together
internally).
(2)
Impedance parameters are specified directly between pins TX/RX A(B)
and TX/RX A(B) of the PCI Enhanced Mini-ACE hybrid.
(3)
It is assumed that all power and ground inputs to the hybrid are
connected.
(4)
The specifications are applicable for both unpowered and powered
conditions.
(5)
The specifications assume a 2-volt rms balanced differential, sinusoidal
input. The applicable frequency range is 75 kHz to 1 MHz.
(6)
Minimum
resistance
and
maximum
capacitance
parameters
are
guaranteed over the operating range, but are not tested.
(7)
Assumes a common mode voltage within the frequency range of dc to 2
MHz, applied to pins of the isolation transformer on the stub side (either
direct or transformer coupled), and referenced to hybrid ground.
Transformer must be a DDC recommended transformer or other
transformer that provides an equivalent minimum CMRR.
(8)
Typical value for minimum intermessage gap time.
Under software
control, this may be lengthened to 65,535 ms - message time, in
increments of 1
s. If ENHANCED CPU ACCESS, bit 14 of Configuration
Register #6, is set to logic “1”, then host accesses during BC Start-of-
Message (SOM) and End-of-Message (EOM) transfer sequences could
have the effect of lengthening the intermessage gap time. For each host
access during an SOM or EOM sequence, the intermessage gap time will
be lengthened by 6 clock cycles. Since there are 7 internal transfers
during SOM, and 5 during EOM, this could theoretically lengthen the
intermessage gap by up to 72 clock cycles; i.e., up to 7.2
s with a 10
MHz clock, 6.0
s with a 12 MHz clock, 4.5 s with a 16 MHz clock, or 3.6
s with a 20 MHz clock.
(9)
For Enhanced BC mode, the typical value for intermessage gap time is
approximately 10 clock cycles longer than for the non-enhanced BC
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相关代理商/技术参数 |
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|---|---|
| BU-62843 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MIL-STD-1553 Components |PCI-Enhanced Mini-ACE? |
| BU-62864 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MIL-STD-1553 Components |PCI-Enhanced Mini-ACE? |
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