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参数资料
| 型号： | BU-62743B3-112S |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128 |
| 封装： | 0.815 X 0.815 INCH, 0.140 INCH HEIGHT, 1 MM PITCH, BGA-128 |
| 文件页数： | 24/93页 |
| 文件大小： | 504K |
| 代理商： | BU-62743B3-112S |
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Data Device Corporation
62743_pre2.DOC.doc
www.ddc-web.com
8-15-01
30
BC Instruction List Pointer Register may be read to determine the current
location of the Instruction List Pointer for the Enhanced BC mode.
BC Control Word/RT Subaddress Control Word Register:
In BC mode,
allows host access to the current word or most recent BC Control Word. The BC
Control Word contains bits that select the active bus and message format,
enable off-line self-test, masking of Status Word bits, enable retires and
interrupts, and specify MIL-STD-1553A or -1553B error handling. In RT mode,
this register allows host access to the current or most recent Subaddress Control
Word.
The Subaddress Control Word is used to select the memory
management scheme and enable interrupts for the current message.
Time Tag Register maintains the value of a real-time clock. The resolution of
this register is programmable from among 2, 4, 8, 16, 32, and 64
s/LSB. The
Start-of-Message (SOM) and End-of-Message (EOM) sequences in BC, RT, and
Message Monitor modes cause a write of the current value of the Time Tag
Register to the stack area of the RAM.
Interrupt Status Register #1 and #2 allow the host processor to determine the
cause of an interrupt request by means of one or two read accesses. The
interrupt events of the two Interrupt Status Registers are mapped to correspond
to the respective bit positions in the two Interrupt Mask Registers. Interrupt
Status Register #2 contains an INTERRUPT CHAIN bit, used to indicate an
interrupt event from Interrupt Status Register #1.
Configuration Registers #3, #4, and #5 are used to enable many of the PCI
Enhanced Mini-ACE’s advanced features that were implemented by the prior
generation products, the ACE and Mini-ACE (Plus). For BC, RT, and MT modes,
use of the ENHANCED MODE enables the various read-only bits in
Configuration Register #1. For BC mode, ENHANCED mode features include
the expanded BC Control Word and BC Block Status Word, additional Stop-On-
Error and Stop-On-Status Set functions, frame auto-repeat, programmable
intermessage gap times, automatic retires, expanded Status Word Masking, and
the capability to generate interrupts following the completion of any selected
message. For RT mode, the enhanced mode features include the expanded RT
Block Status Word, combined RT/Selective Message Monitor mode, internal
wrapping of the RTFAIL* output signal to the RTFLAG* RT Status Word bit; the
double buffering scheme for individual receive (broadcast) subaddresses, and
the alternate (fully software programmable) RT Status Word. For MT mode, use
of the enhanced mode enables the Selective Message Monitor, the combined
RT/Selective Monitor modes, and the monitor triggering capability.
RT/Monitor Data Stack Address Register provides a read/writable indication of
the last data word stored for RT or Monitor modes.
BC Frame Time Remaining Register provides a read-only indication of the time
remaining in the current BC frame. In the enhanced BC mode, this timer may be
相关PDF资料 |
PDF描述 |
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| BU-62743B3-120L | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128 |
| BU-62743B3-120S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128 |
| BU-62743B3-122W | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128 |
| BU-62743B3-130S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128 |
| BU-62743B3-130Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128 |
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参数描述 |
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| BU-62843 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MIL-STD-1553 Components |PCI-Enhanced Mini-ACE? |
| BU-62864 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MIL-STD-1553 Components |PCI-Enhanced Mini-ACE? |
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