参数资料
型号: BU-62743B3-112S
厂商: DATA DEVICE CORP
元件分类: 微控制器/微处理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128
封装: 0.815 X 0.815 INCH, 0.140 INCH HEIGHT, 1 MM PITCH, BGA-128
文件页数: 55/93页
文件大小: 504K
代理商: BU-62743B3-112S
Data Device Corporation
62743_pre2.DOC
www.ddc-web.com
8-15-01
59
RT Command stack 50% rollover, MT data stack 50% rollover, MT command
stack 50% rollover, and RT Circular buffer 50% rollover. Non-message interrupt
events/conditions include time tag rollover, RT address parity error, RAM parity
error, and BIT completed.
Bit 0 of the interrupt vector (interrupt status) word indicates whether the entry is for
a message interrupt event (if bit 0 is logic "1") or a non-message interrupt event (if
bit 0 is logic "0"). It is not possible for one entry on the queue to indicate both a
message interrupt and a non-message interrupt.
As illustrated in Figure 10, for a message interrupt event, the parameter word is a
pointer. The pointer will reference the first word of the RT or MT command stack
descriptor (i.e., the Block Status Word).
For a RAM Parity Error non-message interrupt, the parameter will be the RAM
address where the parity check failed. For the RT address Parity Error, Protocol
Self-test Complete. And Time Tag Rollover non-message interrupts, the parameter
is not used; it will have a value of 0000.
If enabled, an INTERRUPT STATUS QUEUE ROLLOVER interrupt will be
issued when the value of the queue pointer address rolls over at a 64-word
address boundary.
RT COMMAND ILLEGALIZATION
The PCI Enhanced Mini-ACE provides an internal mechanism for RT Command
Word illegalizing. By means of a 256-word area in shared RAM, the host processor
may designate that any message be illegalized, based on the command word T/R
bit, subaddress, and word count/mode code fields. The PCI Enhanced Mini-ACE
illegalization scheme provides the maximum in flexibility, allowing any subset of the
4096 possible combinations of broadcast/own address, T/R* bit, subaddress, and
word count/mode code to be illegalized.
The address map of the PCI Enhanced Mini-ACE’s illegalizing table is illustrated in
Table 53.
相关PDF资料
PDF描述
BU-62743B3-120L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128
BU-62743B3-120S 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128
BU-62743B3-122W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128
BU-62743B3-130S 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128
BU-62743B3-130Y 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128
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