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参数资料
| 型号： | BU9833GUL-WE2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 3/27页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 2KBIT 100KHZ VCSP50L1 |
| 标准包装： | 3,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 2K (256 x 8) |
| 速度： | 400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 6-UFBGA，CSPBGA |
| 供应商设备封装： | VCSP50L1 |
| 包装： | 带卷 (TR) |
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BU9833GUL-W (2Kbit)
● Action timing characteristics (Unless otherwise specified, Ta=-40 ℃ to +85 ℃ , V CC =1.7V to 5.5V)
Datasheet
FAST-MODE
STANDARD-MODE
Parameter Symbol
2.5V ≦ V CC ≦ 5.5V
1.7V ≦ V CC ≦ 5.5V
Unit
Min. Typ. Max. Min. Typ. Max.
SCL frequency
fSCL - - 400 - - 100
kHz
Data clock “HIGH” time
Data clock “LOW” time
SDA, SCL rise time *1
SDA< SCL fall time *1
Start condition hold time
Start condition setup time
Input data hold time
Input data setup time
Output data delay time
Output data hold time
Stop condition setup time
Bus release time before transfer start
Internal write cycle time
Noise removal valid period (SDA, SCL terminal)
WP hold time
WP setup time
WP valid time
tHIGH
tLOW
tR
tF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
tDH
tSU:STO
tBUF
tWR
tI
tHD:WP
tSU:WP
tHIGH:WP
0.6
1.2
-
-
0.6
0.6
0
100
0.1
0.1
0.6
1.2
-
-
0
0.1
1.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.3
0.3
-
-
-
-
0.9
-
-
-
5
0.1
-
-
-
4.0
4.7
-
-
4.0
4.7
0
250
0.2
0.2
4.7
4.7
-
-
0
0.1
1.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.0
0.3
-
-
-
-
3.5
-
-
-
5
0.1
-
-
-
μ s
μ s
μ s
μ s
μ s
μ s
ns
ns
μ s
μ s
μ s
μ s
ms
μ s
ns
μ s
μ s
*1 Not 100% tested.
● Sync data input / output timing
SCL
t R
t F
t HIGH
SCL
t HD :STA
t SU :DAT
t LOW
t HD :DAT
DATA(1)
DATA(n)
SDA
(Input)
t BUF
t PD
t DH
SDA
D1
D0
ACK
ACK
tWR
SDA
(Output)
○ Input read at the rise edge of SCL
○ Data output in sync with the fall of SCL
WP
tSU ： WP
stop condition
ｔ HD ： WP
Figure 1-(a) Sync data input / output timing
SCL
Figure 1-(d) WP timing at write execution
SCL
DATA(1)
DATA(n)
tSU:STA
tHD:STA
tSU:STO
SDA
D1
D0
ACK
ACK
SDA
START BIT
STOP BIT
WP
tHIGH:WP
tWR
SCL
Figure 1-(b) Start – stop bit timing
Figure 1-(e) WP timing at write cancel
At write execution, in the area from the DO taken clock rise of the first
DATA (1), to tWR, set WP=“LOW”
By setting WP “HIGH” in the area, write can be cancelled.
When it is set WP=“HIGH” during tWR, write is forcibly ended, and data
SDA
D0
Write data
(n-th address)
ACK
Stop condition
t WR
Start condition
of address under access is not guaranteed, therefore write it once again.
Figure 1-(c) Write cycle timing
www.rohm.com
? 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
3/24
TSZ02201-0R2R0G100450-1-2
04.SEP.2012 Rev.001
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相关代理商/技术参数 |
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|---|---|
| BU9844GUL-W | 制造商:ROHM 制造商全称:Rohm 功能描述:WL-CSP EEPROM family I2C BUS |
| BU9844GUL-W_10 | 制造商:ROHM 制造商全称:Rohm 功能描述:WL-CSP EEPROM family I2C BUS |
| BU9844GUL-WE2 | 功能描述:电可擦除可编程只读存储器 电可擦除可编程只读存储器 Serial-2Wire 16Kb RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| BU9847GUL-W | 制造商:ROHM 制造商全称:Rohm 功能描述:WL-CSP EEPROM family I2C BUS |
| BU9847GUL-W_10 | 制造商:ROHM 制造商全称:Rohm 功能描述:WL-CSP EEPROM family I2C BUS |
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