参数资料
型号: BU9882FV-WE2
厂商: Rohm Semiconductor
文件页数: 4/21页
文件大小: 0K
描述: IC EEPROM 2KBIT 400KHZ 14SSOP
标准包装: 2,500
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 2K(128 x 8 x 2)
速度: 400kHz
接口: I²C,2 线串口
电源电压: 2.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 14-LSSOP(0.173",4.40mm 宽)
供应商设备封装: 14-SSOP
包装: 带卷 (TR)
BR24C21xxx Series (1K)
● Synchronous data timing
Datasheet
t R
t F
t HIGH
SCL
SCL
t HD :STA
t SU :DAT
t LOW
t HD :DAT
SDA
(IN)
SDA
D0
WRITE DATA(n)
ACK
t WR
t BUF
t PD
STOP CONDITION
START CONDITION
SDA
(OUT)
SCL
SCL
Figure 2.
Write Cycle Timing
START BIT
STOP BIT
t SU :STA
tHD:STA
t SU :STO
SDA
SDA
STOP BIT
START BIT
VCLK
Figure 1. Synchronous Data Timing
? SDA data is latched into the chip at the rising edge of the SCL clock.
? Output data toggles at the falling edge of the SCL clock.
t VSU
WRITE COMMAND
t VHD
Figure 3.
Write Enable Timing
● Transmit-only mode
? After power is on, the BR24C21/F/FJ/FV is in Transmit-Only Mode. In this mode data can be output by providing the clock
to the VCLK pin.
? When the power is on, the SCL pin needs to be set to V CC (High level).
? SDA is at high-impedance during input of the first 9 clocks. At the 10th rising clock edge of VCLK data is output. After
power on, the output data is as follows:
00h address data → 01h address data → 02h address data → …
The address is incremented by one, after every 9 clocks of VCLK. All addresses are output in this mode.
When the counter reaches the last address, the next output data is 00h address data. (See Figure 4.)
? In this mode, the NULL bit (High data) is output between the address data and the next address data. (See Figure 5.)
? The read operation is in Transmit-Only Mode and can be started after the power is stabilized.
tVHIGH tVLOW
Vcc
VCLK
SCL
tVPD
VCLK
1
9
10
SDA
D1
D0
D7
D6
tVPU
ADDRESS n
DATA
NULL BIT
DATA=1
ADDRESS n+1
DATA
SDA
D7
D6
D5
D4
D3
00h ADDRESS DATA
Figure 4.
Transmit Only Mode
Figure 5.
Null Bit
www.rohm.com
? 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
4/18
TSZ02201-0R2R0G100270-1-2
10.Jul.2012 Rev.001
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