![](http://datasheet.mmic.net.cn/200000/BX80525U500512E_datasheet_15053287/BX80525U500512E_18.png)
Pentium
III Processor at 450 MHz, 500 MHz, 533B MHz, 550 MHz, 600/600B MHz
18
Datasheet
Note that the ‘11111’ (all opens) ID can be used to detect the absence of a processor core in a given
connector as long as the power supply used does not affect these lines. Detection logic and pull-ups
should not affect VID inputs at the power source (see Section 7.0).
The VID pins should be pulled up to a TTL-compatible level with external resistors to the power
source of the regulator only if required by the regulator or external logic monitoring the VID[4:0]
signals. The power source chosen must be guaranteed to be stable whenever the supply to the
voltage regulator is stable. This will prevent the possibility of the processor supply going above the
specified VCC
CORE in the event of a failure in the supply for the VID lines. In the case of a DC-to-DC
converter, this can be accomplished by using the input voltage to the converter for the VID line
pull-ups. A resistor of greater than or equal to 10 k
may be used to connect the VID signals to the
converter input. Note that no changes have been made to the physical connector between the
Intel-enabled VRM 8.1 and VRM 8.2 specifications, though pin definitions have changed.
2.7
Processor System Bus Unused Pins
All RESERVED pins must remain unconnected. Connection of these pins to VCC
CORE, VCCL2, VSS, or
to any other signal (including each other) can result in component malfunction or incompatibility
with future Pentium III processors. See Section 5.5 for a pin listing of the processor and the location
of each RESERVED pin.
All TESTHI pins must be connected to 2.5 V via 1-100 k
pull-up resistor.
PICCLK must be driven with a valid clock input and the PICD[1:0] lines must be pulled-up to
2.5 V even when the APIC will not be used. A separate pull-up resistor must be provided for each
APIC data line.
For reliable operation, always connect unused inputs or bidirectional signals to an appropriate
signal level. Unused AGTL+ inputs should be left as no connects; AGTL+ termination is provided
on the processor. Unused active low CMOS inputs should be connected through a resistor to 2.5 V.
Unused active high inputs should be connected through a resistor to ground (V
SS). Unused outputs
can be left unconnected. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system testability.
For unused pins, it is suggested that ~10 k
resistors be used for pull-ups (except for PICD[1:0]
discussed above), and ~1 k
resistors be used as pull-downs.
2.8
Processor System Bus Signal Groups
In order to simplify the following discussion, the Pentium III processor system bus signals have
been combined into groups by buffer type. All Pentium III processor system bus outputs are open
drain and require a high-level source provided externally by the termination or pull-up resistor.
However, the Pentium III processor includes on cartridge termination.
AGTL+ input signals have differential input buffers, which use VREF as a reference signal. AGTL+
output signals require termination to 1.5 V. In this document, the term “AGTL+ Input” refers to the
AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output”
refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
EMI pins may be connected to baseboard ground and/or to chassis ground through zero ohm (0
)
resistors. The 0
resistors should be placed in close proximity to the SC242 connector. The path to
chassis ground should be short in length and have a low impedance.