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参数资料
| 型号： | BX80552360 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 3460 MHz, MICROPROCESSOR, CBGA775 |
| 封装： | LGA-775 |
| 文件页数： | 18/96页 |
| 文件大小： | 1975K |
| 代理商： | BX80552360 |
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Datasheet
25
Electrical Specifications
2.6.2
GTL+ Asynchronous Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS
input buffers. All of these signals follow the same DC requirements as GTL+ signals;
however, the outputs are not actively driven high (during a logical 0 to 1 transition) by
the processor. These signals do not have setup or hold time specifications in relation to
BCLK[1:0].
All of the GTL+ Asynchronous signals are required to be asserted/de-asserted for at
least six BCLKs in order for the processor to recognize the proper signal state. See
Section 2.6.3 for the DC specifications for the GTL+ Asynchronous signal groups. See
Section 6.2 for additional timing requirements for entering and leaving the low power
states.
2.6.3
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads)
unless otherwise stated. All specifications apply to all frequencies and cache sizes
unless otherwise stated.
Table 10.
GTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes1
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
VIL
Input Low Voltage
0.0
GTLREF – (0.10 * VTT)V
2, 3
2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3. The VTT referred to in these specifications is the instantaneous VTT.
VIH
Input High Voltage
GTLREF + (0.10 * VTT)VTT
V
4, 5, 3
4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5. VIH and VOH may experience excursions above VTT. However, input signal drivers must comply with the
signal quality specifications.
VOH
Output High Voltage
0.90*VTT
VTT
V
3, 5
IOL
Output Low Current
N/A
VTT_MAX/
[(0.50*RTT_MIN)+(RON_MIN)]
A-
ILI
Input Leakage
Current
N/A
± 200
A
6
6. Leakage to VSS with land held at VTT.
ILO
Output Leakage
Current
N/A
± 200
A
7
7. Leakage to VTT with land held at 300 mV.
RON
Buffer On Resistance
6
12
Ω
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