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参数资料
| 型号： | C163-L |
| 厂商： | SIEMENS AG |
| 英文描述： | 16-bit CMOS Single-Chip Microcontroller |
| 中文描述： | 16位CMOS单片机 |
| 文件页数： | 12/68页 |
| 文件大小： | 625K |
| 代理商： | C163-L |
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11Aug98@14:48h Intermediate Version
Semiconductor Group
10
1998-08
C163-L
External Bus Controller
All of the external memory accesses are performed by a particular on-chip External Bus Controller
(EBC). It can be programmed either to Single Chip Mode when no external memory is required, or
to one of four different external memory access modes, which are as follows:
– 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed
– 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on
PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for
input/output.
Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-
State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user
the adaption of a wide range of different types of memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx /
BUSCONx) which allow to access different resources with different bus characteristics. These
address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and
BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows
are controlled by BUSCON0.
Up to 5 external CS signals (4 windows plus default) can be generated in order to save external glue
logic. Access to very slow memories is supported via a particular ‘Ready’ function.
A HOLD/HLDA protocol is available for bus arbitration and allows to share external resources with
other bus masters. The bus arbitration is enabled by setting bit HLDEN in register SYSCON. After
setting HLDEN once, pins P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the
EBC. In Master Mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to ’1’ the
Slave Mode is selected where pin HLDA is switched to input. This allows to directly connect the
slave controller to another master controller without glue logic.
For applications which require less than 16 MBytes of external memory space, this address space
can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no
address lines at all. It outputs all 8 address lines, if an address space of 16 MBytes is used.
Note:
When the on-chip SSP Module is to be used the segment address output on Port 4 must be
limited to 4 bits (ie. A19...A16) in order to enable the alternate function of the SSP interface
pins.
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