Fast External Interrupt 0 Input
Fast External Interrupt 1 Input
Fast External Interrupt 2 Input
Fast External Interrupt 3 Input
Fast External Interrupt 4 Input
Fast External Interrupt 5 Input
Fast External Interrupt 6 Input
Fast External Interrupt 7 Input
11Aug98@14:48h Intermediate Version
Semiconductor Group
7
1998-08
C163-L
P6
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
82
83
84
85
86
87
88
89
IO
O
O
O
O
O
I
I/O
O
Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for
input or output via direction bits. For a pin configured as input, the
output driver is put into high-impedance state. Port 6 outputs can be
configured as push/pull or open drain drivers.
The Port 6 pins also serve as bus interface signals:
CS0
Chip Select 0 Output
CS1
Chip Select 1 Output
CS2
Chip Select 2 Output
CS3
Chip Select 3 Output
CS4
Chip Select 4 Output
HOLD
External Master Hold Request Input
HLDA
Hold Acknowledge Output or Input
(Master mode: O, Slave mode: I)
BREQ
Bus Request Output
P2
P2.8
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
90
91
92
93
94
95
96
97
IO
I
I
I
I
I
I
I
I
Port 2 is an 8-bit bidirectional I/O port. It is bit-wise programmable for
input or output via direction bits. For a pin configured as input, the
output driver is put into high-impedance state. Port 2 outputs can be
configured as push/pull or open drain drivers.
The Port 2 pins also serve as fast external interrupt inputs:
EX0IN
EX1IN
EX2IN
EX3IN
EX4IN
EX5IN
EX6IN
EX7IN
OWE
40
I
Oscillator Watchdog Enable. This pin enables the PLL when high or
disables it when low (e.g. to disable the OWD for testing purposes.
An internal pullup device holds this input high if nothing is driving it.
Note
:
The input voltage at pin OWE must not exceed 12.6 V.
For 3 V operation pin OWE must be driven low.
V
DD
7, 28,
38, 49,
69, 78
-
Digital Supply Voltage:
+ 5 V or +3 V during normal operation and idle mode.
≥
2.5 V during power down mode
Digital Ground.
V
SS
4, 27,
39, 50,
70, 77
-
Pin Definitions and Functions
(cont’d)
Symbol Pin
Numb.
TQFP
Input
Out-
put
Function