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参数资料
| 型号： | C163-L |
| 厂商： | SIEMENS AG |
| 英文描述： | 16-bit CMOS Single-Chip Microcontroller |
| 中文描述： | 16位CMOS单片机 |
| 文件页数： | 13/68页 |
| 文件大小： | 625K |
| 代理商： | C163-L |
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11Aug98@14:48h Intermediate Version
Semiconductor Group
11
1998-08
C163-L
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit
(ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide
unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C163-L’s instructions can be executed in just one
machine cycle which requires 80 ns at 25-MHz CPU clock. For example, shift and rotate instructions
are always processed during one machine cycle independent of the number of bits to be shifted. All
multiple-cycle instructions have been optimized so that they can be executed very fast as well:
branches in 2 cycles, a 16
×
16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles.
Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of
repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
Figure 4
CPU Block Diagram
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