参数资料
型号: C8051F018R
厂商: Silicon Laboratories Inc
文件页数: 63/154页
文件大小: 0K
描述: IC 8051 MCU 16K FLASH 64TQFP
标准包装: 1
系列: C8051F018
核心处理器: 8051
芯体尺寸: 8-位
速度: 25MHz
连通性: SMBus(2 线/I²C),SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,温度传感器,WDT
输入/输出数: 32
程序存储器容量: 16KB(16K x 8)
程序存储器类型: 闪存
RAM 容量: 1.25K x 8
电压 - 电源 (Vcc/Vdd): 2.8 V ~ 3.6 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-TQFP
包装: 剪切带 (CT)
其它名称: 336-1048-1
C8051F018
C8051F019
1.7.
Analog to Digital Converter
The C8051F018/9 have an on-chip 10-bit SAR ADC with a 9-channel input multiplexer.
With a maximum
throughput of 100ksps, the ADC offers true 10-bit accuracy with an INL of
1LSB. The ADC has a maximum
throughput of 100ksps. There is also an on-board 15ppm voltage reference, or an external reference may be used
via the VREF pin.
The ADC is under full control of the CIP-51 microcontroller via the Special Function Registers. One input channel
is tied to an internal temperature sensor, while the other eight channels are available externally. Each pair of the
eight external input channels can be configured as either two single-ended inputs or a single differential input. The
system controller can also put the ADC into shutdown to save power.
Conversions can be started in four ways; a software command, an overflow on Timer 2, an overflow on Timer 3, or
an external signal input. This flexibility allows the start of conversion to be triggered by software events, external
HW signals, or convert continuously. A completed conversion causes an interrupt, or a status bit can be polled in
software to determine the end of conversion.
The resulting 10-bit data word is latched into two SFRs upon
completion of a conversion. The data can be right or left justified in these registers under software control.
Compare registers for the ADC data can be configured to interrupt the controller when ADC data is within a
specified window. The ADC can monitor a key voltage continuously in background mode, but not interrupt the
controller unless the converted data is within the specified window.
Figure 1.9. ADC Diagram
100ksps
SAR
ADC
Control & Data
SFR's
SFR Bus
+
-
+
-
+
-
9-to-1
AMUX
(SE or
DIFF)
+
-
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
TEMP
SENSOR
VREF
REF
Rev. 1.2
16
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