参数资料
型号: C8051F226R
厂商: Silicon Laboratories Inc
文件页数: 83/146页
文件大小: 0K
描述: IC 8051 MCU 8K FLASH 48TQFP
标准包装: 1
系列: C8051F2xx
核心处理器: 8051
芯体尺寸: 8-位
速度: 25MHz
连通性: SPI,UART/USART
外围设备: 欠压检测/复位,POR,WDT
输入/输出数: 32
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
RAM 容量: 1.25K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.6 V
数据转换器: A/D 32x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-TQFP
包装: 剪切带 (CT)
其它名称: 336-1010-1
C8051F2xx
Rev. 1.6
41
6.2.
ADC Modes of Operation
The ADC has a maximum conversion speed of 100 ksps. The ADC conversion clock is derived from the
system clock. The ADC conversion clock is derived from a divided version of SYSCLK. Divide ratios of 1,
2, 4, 8, or 16 are supported by setting the ADCSC bits in the ADC0CF Register. This is useful to adjust
conversion speed to accommodate different system clock speeds.
A conversion can be initiated in one of two ways, depending on the programmed states of the ADC Start of
Conversion Mode bits (ADSTM1, ADSTM0) in ADC0CN. Conversions may be initiated by:
1.
Writing a 1 to the ADBUSY bit of ADC0CN;
2.
A Timer 2 overflow (i.e. timed continuous conversions).
Writing a 1 to ADBUSY provides software control of the ADC whereby conversions are performed "on-
demand". During conversion, the ADBUSY bit is set to 1 and restored to 0 when conversion is complete.
The falling edge of ADBUSY triggers an interrupt (when enabled) and sets the ADCINT interrupt flag in the
ADC0CN register. Note: When conversions are performed "on-demand", the ADCINT flag, not ADBUSY,
should be polled to determine when the conversion has completed. Converted data is available in the ADC
data word register, ADC0H.
The ADCTM bit in register ADC0CN controls the ADC track-and-hold mode. In its default state, the ADC
input is continuously tracked, except when a conversion is in progress. Setting ADCTM to 1 allows one of
two different low power track-and-hold modes to be specified by states of the ADSTM1-0 bits (also in
ADC0CN):
1.
Tracking begins with a write of 1 to ADBUSY and lasts for 3 SAR clocks;
2.
Tracking starts with an overflow of Timer 2 and lasts for 3 SAR clocks.
Tracking can be disabled (shutdown) when the entire chip is in low power standby or sleep modes.
Figure 6.2. 12-Bit ADC Track and Conversion Example Timing
12
345
678
9
10 11 12 13 14 15 16
CNVSTR
(ADSTM[1:0]=10)
ADCTM=1
Track
Convert
Low Power Mode
ADCTM=0
Track Or Convert
Convert
Track
Low Power or
Convert
Timer2, Timer3 Overflow;
Write 1 to ADBUSY
(ADSTM[1:0]=00, 01, 11)
ADCTM=1
Track
Convert
Low Power Mode
ADCTM=0
Track or Convert
Convert
Track
Low Power or
Convert
A. ADC Timing for External Trigger Source
B. ADC Timing for Internal Trigger Sources
SAR Clocks
12
3456
789
10 11 12 13 14 15 16 17 18 19
12
3456
789
10 11 12 13 14 15 16
SAR Clocks
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