- 您现在的位置：买卖IC网 > Datasheet目录317 > C8051F912DK (Silicon Laboratories Inc)KIT DEV FOR C8051F91X/C8051F90X Datasheet资料下载
参数资料
| 型号： | C8051F912DK |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 21/25页 |
| 文件大小： | 0K |
| 描述： | KIT DEV FOR C8051F91X/C8051F90X |
| 产品培训模块： | C8051F9xx Lower Power MCUs |
| 视频文件： | Designing for Low Power Operation |
| 特色产品： | C8051F91x/0x MCU Series Development Kit |
| 标准包装： | 1 |
| 类型： | MCU |
| 适用于相关产品： | C8051F91x/0x |
| 所含物品： | 板，电池，线缆，CD，电源适配器，USB 调试适配器 |
| 产品目录页面： | 626 (CN2011-ZH PDF) |
| 其它名称： | 336-1854 |
C8051F91x/90x
11. When the missing clock detector is enabled, why does the MCU reset if I switch from the default
system clock (Low Power Oscillator divided by 8) to smaRTClock divided by 1?
Background:
—The missing clock detector will trigger a reset if the system clock period exceeds 100 μs.
—Switchover between clock sources occurs in 1 clock cycle of the slowest clock.
—Changing the clock divide value requires up to 128 cycles of the undivided clock source.
Since the clock source change occurs in a single cycle and the clock divide change can take up to 128
cycles, the system clock will be set to the new clock source divided by the old divide value for a brief
period of time. In this example, the actual system clock will be 4.096 kHz for up to 128 cycles of the
undivided clock source. This causes the missing clock detector to time out and reset the MCU.
The proper way of changing the system clock when both the clock source and the clock divide value are
being changed is as follows:
If switching from a fast “undivided” clock to a slower “undivided” clock:
a. Change the clock divide value.
b. Poll for CLKRDY > 1.
c. Change the clock source .
If switching from a fast “undivided” clock to a slower “undivided” clock:
d. Change the clock source .
e. Change the clock divide value.
f. Poll for CLKRDY > 1.
12. Why is the MCU pre-maturely released from reset when using a wall supply with a slow rise time?
The maximum VDD Ramp Time is specified at 3 ms. If the power supply ramp takes longer than 3 ms to
reach 0.9 V, then the device may be released from reset before the supply has reached the minimum
operating voltage. The slow ramp time (>3 ms) can occur when using a bench power supply that does not
have an output enable switch.
Rev. 0.2
21
相关PDF资料 |
PDF描述 |
|---|---|
| C8051F930-TB | BOARD TARGET/PROTO W/C8051F930 |
| C8051T610DB24 | DAUGHTER BOARD T610 24QFN SOCKET |
| C8051T630DB20 | BOARD SOCKET DAUGHTER 20-QFN |
| CAN-100 | BOARD EVAL RS232 100QFP |
| CANADAPT28 | KIT ADAPTER CANDEMOBOARD 28PLCC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| C8051F912-GDI | 功能描述:8位微控制器 -MCU 16kB Flash MCU RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| C8051F912-GM | 功能描述:8位微控制器 -MCU 16KB 12ADC 24QFN RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| C8051F912-GMR | 功能描述:8位微控制器 -MCU 16KB 12ADC RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| C8051F912-GU | 功能描述:8位微控制器 -MCU 16KB 12ADC 24QSOP RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| C8051F912-GUR | 功能描述:8位微控制器 -MCU 16KB 12ADC RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
发布紧急采购，3分钟左右您将得到回复。