![](http://datasheet.mmic.net.cn/260000/C9822EQ_datasheet_15873007/C9822EQ_14.png)
Direct Rambus
III Clock Generator
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07093 Rev. **
05/04/2001
Page 14 of 19
APPROVED PRODUCT
C9822
AC Operating Conditions
Characteristic
Refclk Input Cycle Time
Faster speed bin for Refclk input cycle time
a
Input Cycle-to-cycle jitter
b
Input Duty Cycle over 10,000 cycles
Input Frequency of Modulation
Modulation index for triangular modulation
Modulation index for non-triangular modulation
Phase Detector Input Cycle time at PclkM and
SynclkN
Initial Phase Error at Phase Detector Inputs (required
range of phase aligner)
Phase Detector Input Duty Cycle over 10,000 Cycles
Input Slew Rate (measured at 20% - 80% of input
voltage) for PclkM, SynclkN, and Refclk
Input Capacitance at PclkM, SynclkN, and Refclk
e
Input Capacitance Matching at PclkM and SynclkN
e
Input Capacitance at Scalable CMOS Pins (excluding
PclkM, SynclkN, and Refclk)
e
a. Faster speed bin for future systems (not a requirement now), and applicable for V
DDI,R
>1.7V only
b. Refclk jitter measured at V
DDI,R
(nom)/2
c. If input modulation is used; input modulation is allowed but not required.
d. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream
tracking skew, which cannot exceed the skew generated by the specified 0.6% triangular modulation. Typically, the
amount of allowed non-triangular modulation is about 0.5%.
e. Capacitance measured at Freq = 1 MHz, DC bias = 0.9V, and V
AC
<100mV
Symbol
Min
10
6
a
Typ
-
-
-
-
-
-
-
-
Max
40
40
250
60%
33
0.6
0.5
d
100
Units
t
CYCLE,IN
nS
nS
pS
t
J,IN
D
CIN
f
MIN,IN
P
M,IN
-
c
40%
30
-
-
30
t
CYCLE
kHz
%
%
nS
C
c
t
CYCLE, PD
t
ERR,INIT
-0.5
-
0.5
t
CYCLE,PD
D
CIN,PD
t
I,SR
25%
1
-
-
75%
4
t
CYCLE,PD
V/nS
C
IN,PD
C
IN,PD
C
IN,CMOS
-
-
-
-
-
-
7
pF
pF
pF
0.5
10
Table 12: AC Operating Conditions