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参数资料
| 型号： | C9822EQ |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | 单时钟驱动器| SSOP封装| 24针|塑料 |
| 文件页数： | 8/19页 |
| 文件大小： | 123K |
| 代理商： | C9822EQ |
Direct Rambus
III Clock Generator
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07093 Rev. **
05/04/2001
Page 8 of 19
APPROVED PRODUCT
C9822
State Transitions
The clock source has three fundamental operating states. Figure 5 shows the state diagram with each transition
labeled A through J. Note that the clock source output need NOT be glitch-free during state transitions.
Figure 5: Clock Source State Diagram
Upon powering up the device, the device can enter any state, depending on the settings of the control signals
PwrDnB and StopB.
In Powerdown mode, the clock source is powered down with the control signal, PwrDnB, equal to 0. The control
signals S0, S1, and S2 must be stable before power is applied to the device, and can only be changed in
Powerdown mode (PwrDnB=0). The reference inputs, VddIR and VddIPd, may remain on or may be grounded
during the Powerdown mode.
The control signals Mult0, Mult1 can be used in two ways. If they are changed during Powerdown mode, then the
Powerdown transition timings determine the settling time of the DRCG. However, the Mult0 and Mult1 control
signals can also be changed during Normal mode. When the Mult control signals are “hot swapped” in this manner,
the Mult transition timings determine the settling time of the DRCG.
In Clk Stop mode, the clock source is on, but the output is disabled (StopB de-asserted). The VddIPD reference
input may remain on or may be grounded during the Clk Stop mode. The VddIR reference input must remain on
during the Clk Stop mode.
Normal
Powerdown
Clk Stop
Vdd turn-on
Vdd turn-on
Vdd turn-on
G
J
F
E
H
C
D
A
B
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