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| 型号： | CA95C09-20CN |
| 元件分类： | 加密电路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 36/42页 |
| 文件大小： | 180K |
| 代理商： | CA95C09-20CN |
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Tundra Semiconductor Corporation
CA95C68/18/09
Tundra Semiconductor Corporation
3-65
CA95C68/18/09 NOTES
This listing describes known operating variants between the
CA95C68/18/09 devices and both the AMD AM9568/18 and
VLSI VM009 devices. Also contained here are some
CA95C68/18/09 operating idiosyncrasies.
1)
CA95C68/18/09 Reset: The CA95C68/18/09 device
does not operate in the default mode of operation until
one of the reset operations are performed on it. Either a
hardware reset, a software reset, or a write to the Mode
Register must be performed before beginning to
program the CA95C68/18/09 to ensure that the device is
operating in the default mode.
2)
CA95C68/18/09 Direct Control Mode: When the
CA95C68/18/09 is programmed for Direct Control
Mode (DCM) operation, the Input and Output Register
address and
must be manually latched immediately
before or immediately after DCM is entered. The device
does not automatically address the Input and Output
Registers (Address 0) when DCM is entered. This
should be done before any operations are performed.
3)
CA95C68/18/09 Busy Bit in CFB-8 Cipher Mode:
When the CA95C68/18/09 is programmed for eight bit
cipher feedback (CFB-8), ciphering in either
Multiplexed Control or Direct Control Mode of
operation, the Busy bit (bit 5 in the Status Register) and
the
pin (AUX2-
in DCM) go active before the
Input Register is addressed. The Busy bit and the
pin go active immediately after the Mode Register is
programmed for the CFB-8 cipher type. This bit (and
pin in DCM) is not of great importance and should be
ignored in this mode of operation.
4)
Synchronization for CA95C68/18/09 and VM009
Read/Write: Compared to the VLSI VM009 device, the
CA95C68/18/09 has a narrower window in which the
read and write strobes must synchronize to the clock
input. The CA95C68/18/09 AC parameter in question is
t45 which is specied as a minimum of 2ns and a
maximum of tc-25ns. Therefore, the CA95C68/18/09
read and write strobes must be driven HIGH between 2
and 15ns after the falling edge of the clock if you are
using the DCP at 25MHz. With the VLSI device, the
read and write synchronization occurs on the rising edge
of the clock and there is only a 4ns region in which the
strobes can not go HIGH for any clock frequency.
5)
Clock Frequency: The clock input frequency for the
various devices are:
AM9568
1.0 MHz to 4.0 MHz
AM9518
1.0 MHz to 3.1 MHz
CA95C68/18/09
0 MHz to 33MHz
VM009
0 MHz to 33 MHz
6)
One-Bit Cipher Feedback Mode: This is a mode of
encryption supported by the CA95C68/18/09 that the
AMD and VLSI devices do not provide.
MCS
BSY
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