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参数资料
| 型号： | CA95C09-10CT |
| 元件分类： | 加密电路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP44 |
| 封装： | TQFP-44 |
| 文件页数： | 1/42页 |
| 文件大小： | 180K |
| 代理商： | CA95C09-10CT |
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CA95C68/18/09
DES DATA CIPHERING PROCESSORS (DCP)
Tundra Semiconductor Corporation
3-25
Table 3-1 : CA95C68/18/09 Data Transfer Rates
Product
Code
Data Transfer Rates
System Clock
(MHz)
ECB or CBC Mode
(Mbytes/s)
CFB-8 Mode
(Mbytes/s)
CFB-1 Mode
(Mbits/s)
CA95Cxx – 5
2.22
0.27
5
CA95Cxx – 10
4.44
0.55
10
CA95Cxx – 16
7.10
0.88
16
CA95Cxx – 20
8.88
1.11
20
CA95Cxx – 25
11.11
1.38
25
CA95Cxx-33
14.81
1.85
33
Encrypts/Decrypts data using National Bureau
of Standards Data Encryption Standard (DES)
High speed, pin and function compatible
version of industry standard AMD AM9568,
AM9518 and VLSI VM009
Supports four standard ciphering modes:
Electronic Code Book (ECB), Cipher Block
Chaining (CBC), as well as 1 and 8 bit Cipher
Feedback (CFB)
Data rates greater than 11 Mbytes per second
(25 MHz) in ECB or CBC modes
Three separate registers for encryption,
decryption and master keys improve system
security and throughput by eliminating the need
to reload keys frequently
Fully static CMOS, TTL I/O compatible device,
operates at up to 33MHz
Low power consumption allows battery back-up
of internal key registers
Three separate programmable ports (master,
slave and key data)
Available in 44 pin PLCC and 40 pin PDIP and 44
pin TQFP packages
3
3.2
CA95C68/18/09
The Tundra Semiconductor Corporation CA95C68/18/09
DES Data Ciphering Processors (DCPs) implement the
National Bureau of Standards Data Encryption Standard
(DES), FIPS PUB 46 (1-15-1977). The DCPs were designed
to be used in a variety of environments where computer and
communications security is essential.
The DCPs provide a high throughput rate (up to 14 Mbytes
per second) using ECB or CBC modes of operation. The
DCPs provide a unique 1 bit CFB mode as well as the
standard 8 bit mode. Separate ports for key input, clear data
and enciphered data enhance security for your application.
The system communicates with the DCP using commands
entered in the Master Port or through auxiliary control lines.
Once the DCP is set up, data can ow through at high speeds
since input, output and ciphering activities are performed
concurrently. External DMA control can easily be used to
enhance throughput in many system congurations.
The CA95C68 is designed to interface directly to the
iAPX86, 88 CPU bus, and with a minimum of external logic,
to the 2900 and 8051 families of processors. The CA95C18
is designed to interface directly with Z8000, 68000 type bus
interfaces.
The CA95C09 may be congured to behave as either the
CA95C68 or the CA95C18 (see OPTION pin in Table 3-2),
the only difference being the order of the signal names on
the device package.
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