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参数资料
| 型号： | CA95C09-10CT |
| 元件分类： | 加密电路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP44 |
| 封装： | TQFP-44 |
| 文件页数： | 17/42页 |
| 文件大小： | 180K |
| 代理商： | CA95C09-10CT |
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CA95C68/18/09
Tundra Semiconductor Corporation
3-48
Tundra Semiconductor Corporation
REGISTER DESCRIPTION
Description section. In this conguration,
gives the
status of the Input Register and
the Output Register.
Both the Master and Slave Ports are available for input and
output operations when the Conguration bits are set to one
of the dual port congurations (M3,M2 = 00 or 01). When
M3,M2 = 01 (the default conguration), the Master Port
handles clear data while the Slave Port handles ciphered
data. Conguration M3,M2 = 00 reverses this assignment.
The data direction at any particular moment is controlled by
the Encrypt/Decrypt bit (M4).
The Encrypt/Decrypt bit instructs the DCP algorithm
processor to encrypt or decrypt the data from the Input
Register using the ciphering method specied by the Cipher
Type bits. The Encrypt/Decrypt bit also controls the data
ow direction within the DCP. For example, when the
Encrypt/Decrypt bit is “1” (encrypt) and the Conguration
bits are “01” (Dual Port, Master Clear, Slave Encrypted),
clear data will enter the DCP through the Master Port and
encrypted data will be removed from the Slave Port. When
the Encrypt/Decrypt bit is set to “0” (decrypt), the direction
of data ow reverses.
The CFB-1 Mask Direction bit (M5) determines the direction
in which the Mask Register's bits and the input data are
interpreted. When the CFB-1 Mask Direction bit is set to “0”
the DCP will read the Mask Direction and data to be
ciphered from most signicant bit (MSB) to least signicant
bit (LSB). When the CFB-1 Mask Direction bit is set to “1”
the DCP will read the Mask Register and data from LSB to
MSB. The CFB-1 Mask Direction bit is only accessible
when the DCP is set to 1-bit Cipher Feedback mode via the
Mode Register.
The CFB-1 Default Output bit (M6) denes the sense of
output bits which are masked off in the Mask Register. If the
Default Output bit is set to “1” then output bits, which are
masked (not used), will be set to “1”. If the Default Output
bit is cleared to “0” then output bits, which are masked (not
used), will be cleared to “0”.
Mask Register
The 8-bit read/write Mask Register determines which Input
and Output Register bits are signicant during One-bit
Cipher Feedback mode (CFB-1). If any Mask Register bit is
set to “1” then the corresponding bit of the Input Register
will be used as an input to the one-bit cipher feedback
encryption/decryption process and its one bit result will
likewise be placed in the corresponding bit of the Output
Register. If any Mask Register bit is cleared to “0” then the
corresponding bit of the Input Register will be ignored.
MFLG
SFLG
The registers in the DCP which can be directly addressed
through the Master Port are shown with their addresses in
Table 3-7. A brief description of these registers and others
not directly accessible is given below.
Table 3-7 : Master Port Register Address
Mode Register
Figure 3-16 shows the bit assignments in this 7-bit read/write
register. The Cipher Type bits (M1, M0) indicate to the DCP
which ciphering algorithm is to be used. After a reset, the
Cipher Type defaults to the Electronic Code Book.
Conguration bits (M3, M2) indicate which data ports are to
be associated with the Input and Output Registers and ags.
When these bits are set to the Single Port Master Only
conguration (M3, M2=10), the Slave Port is disabled and
no manipulation of Slave Port Chip Select (
) or Slave
Port Data Strobe (
) can cause data movement through
the Slave Port. All data transfers are accomplished through
the Master Port, as described more fully in the Functional
C/K
Cipher
Type
MP2 MP1 9568 9568
MR/W
9518
Register
Addressed
0
all
0
1
0
Input
Register
0
all
0
1
0
Output
Register
0
all
0
1
0
Command
Register
0
all
0
1
0
1
0
Status
Register
0
ECB/
CBC/
CFB-
8
1
0
1
0
Input
Register
0
ECB/
CBC/
CFB-
8
1
0
1
0
Output
Register
0
CFB-
1
0
X
0
Mask
Register
0
all
1
X
0
Mode
Register
X
all
X
1
No Register
Accessed
1
all
X
1
0
Input
Register
1
all
X
0
1
0
Output
Register
MRD
MWR
MCS
SCS
SDS
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