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参数资料
| 型号： | CA95C09-10CT |
| 元件分类： | 加密电路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP44 |
| 封装： | TQFP-44 |
| 文件页数： | 40/42页 |
| 文件大小： | 180K |
| 代理商： | CA95C09-10CT |
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Tundra Semiconductor Corporation
CA95C68/18/09
Tundra Semiconductor Corporation
3-31
30
33
27
I
Slave Port Chip Select: This active LOW signal is logically combined with
the Slave Port Data Strobe (
) to facilitate Slave Port data transfers in a
bus environment.
is not latched internally, and may be tied
permanently LOW without impairing Slave Port operation.
29
32
26
I
Slave Port Data Strobe: This active LOW input, in conjunction with Slave
Port Chip Select (
) LOW indicates to the DCP that valid data is on the
SP7-SP0 lines for an input operation, or that data is to be driven onto SP7-
SP0 lines for output. The direction of data ow is determined by Control bits
in the Mode Register. (See Register Description).
31
34
35
29
O
Slave Port Flag: This active LOW output indicates the state of either the
Input Register or the Output Register, depending on the Mode Register
conguration. In single port conguration,
will go active whenever
the Output Register is not empty during normal processing. In dual port
conguration,
will reect the content of whichever register is
associated with the Slave Port. If the Input Register is assigned to the Slave
Port,
will go active whenever the Input Register is not full, once any
of the Start commands has been entered;
will be forced inactive if
any other command is entered. Conversely, if the Slave Port is assigned to
the Output Register,
will go active whenever the Output Register is
not empty.
AUX7-AUX0
32-35
9-6
36-39
10-7
36-39
10-7
30-33
4-1
I/O
Auxiliary Port Bus: In Multiplexed Control Mode (C/K LOW), these eight
lines form a key byte input port which may be used to enter the Master and
Session Keys. The Master Key can only be entered through this port but
Session Keys may alternatively be entered via the Master Port. AUX0 is the
low-order bit, and is considered to be the Parity bit in key bytes. The most
signicant byte of the key is entered rst. When the DCP is operated in
Direct Control Mode, (C/K HIGH), the Auxiliary Port's key-entry function is
disabled and ve of the eight lines become direct control/status lines for
interfacing to high-speed microprogrammed controllers. In this case, AUX0,
AUX1 and AUX4 have no function (they may be tied HIGH) and the other pins
are dened on the following pages.
AUX5 –S/S
34
38
32
I
Start/Stop: In Direct Control Mode, when this pin goes LOW (Stop) the DCP
will follow the sequence that would normally occur when a Stop Command is
entered. Conversely, when this input goes HIGH, a sequence equivalent to a
Start Encryption or Start Decryption command will be followed. At the time
AUX5-S/S goes HIGH, the level on AUX6-E/D selects either the Start
Encryption or Start Decryption ciphering operation.
AUX6 –E/D
33
37
31
I
Encrypt/Decrypt: In Direct Control Mode, this input species whether the
ciphering algorithm is to encrypt (E/D HIGH) or decrypt (E/D LOW) when
AUX5-S/S goes HIGH to initiate a normal data ciphering operation.
When AUX7-K/D goes HIGH, initiating entry of key bytes, the level on AUX6-
E/D species whether the bytes are to be written into the E Key Register (E/D
HIGH) or the D Key Register (E/D LOW).
The AUX6-E/D input is not latched internally, and must be held constant
whenever one or more of AUX5-S/S, AUX7-K/D, AUX2-
, or AUX3-
are
active. Corrupted data in the internal registers will occur if the proper level on
AUX6-E/D is not maintained during loading or ciphering operations.
Table 3-2 : Pin Description Cont'd
Symbol
95C68/18
95C09
TYPE
Name and Function
PDIP
PLCC
TQFP
SCS
SDS
SCS
SDS
SCS
SFLG
BSY
CP
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