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参数资料
| 型号： | CA95C09-10CT |
| 元件分类： | 加密电路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP44 |
| 封装： | TQFP-44 |
| 文件页数： | 15/42页 |
| 文件大小： | 180K |
| 代理商： | CA95C09-10CT |
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CA95C68/18/09
Tundra Semiconductor Corporation
3-46
Tundra Semiconductor Corporation
All these sequences are identical internally, except that
loading the Mode Register doesn't subsequently reset the
Mode Register. Once the reset process starts, the DCP is
unable
to
respond
to
any
further
commands
for
approximately ve clock cycles. If a power-up reset is used,
the rising edge of the reset signal should not occur until
approximately 1 ms after VDD has reached the normal
operating voltage. This delay time is required for internal
nodes to stabilize.
Master Port Read/Write Timing
The DCP's Master Port is designed to operate with
multiplexed address-data buses. The Master Port can be
optimized to interface with either a Latched Address Enable
(CA95C68) or a Strobed (CA95C18) microprocessor.
Several features of the CA95C68 interface should be
stressed.
The level on Master Port Chip Select (
) is latched
internally on the falling edge of Master Port Address
Latch Enable (MALE) in Multiplexed Control Mode only.
This relieves external address decode circuitry of the
responsibility for latching chip select at address time.
The levels on MP1, MP2 are also latched internally on the
falling edge of MALE and are subsequently decoded to
enable reading and writing of the DCP's internal registers
(Mode, Command, Status, Mask, Input and Output).
Again, this eliminates the need for external address
latching and decoding. The Mask Register is only
accessible when the DCP is programmed for one-bit CFB
mode via the Mode Register's Cipher Type bits.
Data transfers through the Master Port are controlled by
the levels and transitions on the Master Port Read (
)
and Master Port Write (
) pins. Master Port data
transfers do not disturb either the chip-select or address
latches, so that once the DCP and a particular register have
been selected, unlimited writing and reading of that
register can be done without intervening address cycles.
Given the required transfer control external to the DCP,
this feature could greatly speed up loading keys and data.
The CA95C18 interface is similar with the following
exceptions:
The level on
is latched internally on the rising edge
of
in Multiplexed Control Mode only.
The levels on MP1, MP2 are also latched internally on the
rising edge of
and are then decoded to enable reading
and writing of internal registers.
Data transfers through the Master Port are controlled by
Master Port Data Strobe (
) and Master Port
Read/Write (MR/W). The chip-select and address latches
MCS
MRD
MWR
MCS
MAS
MDS
aren't affected by data transfers. Any number of reads or
writes to this selected register can be accomplished without
intervening address cycles.
Loading Key and Initialization Vector (IV) Registers
The Key and Initialization Vector Registers are not directly
addressable through any of the DCP's ports, therefore keys and
vector data must be loaded through “command data
sequences” (see Command Description Section). Most of the
commands recognized by the DCP are of this type: a load or
read command is written to the Command Register through the
Master Port; the command processor responds by asserting the
Command Pending bit in the Status Register; the user then
either writes eight bytes of key or initial vector data through
the Master or Auxiliary Port, as selected by the specic
command, or reads eight bytes of initial vector data from the
Master Port.
In Direct Control Mode, only the E Key and D Key Registers
can be loaded; the M Key and IV Registers are inaccessible.
Loading the E and D Key Registers is accomplished by
asserting the proper state on the AUX6-E/D input (HIGH for E
Key, LOW for D Key) and subsequently raising the AUX7-K/D
input, indicating that key loading is required. The command
processor will assert the AUX3-
(Command Pending)
signal, then the eight key bytes may be written through the
Master Port to the appropriate register. In Multiplexed Control
Mode, all Key and Initial Vector Registers, except the Master
(M) Key, may be loaded with encrypted, as well as clear, data.
Before loading an encrypted key or initial vector, the clear
Master Key must rst be loaded through the Auxiliary Port. If
the operation is a Load Encrypted command, the subsequent
data is written to either the Master or Auxiliary Port and is
routed rst to the Input Register and decrypted before being
stored in the specied Key or Initial Vector Register. After
loading the last byte of an encrypted key or initial vector, no
reading or writing of internal registers is allowed for the
subsequent 60 clock cycles.
Parity Checking of Keys
Key bytes are considered to contain seven bits of key
information and one Parity bit. By DES designation, the low-
order bit is the Parity bit. The parity checking circuit is enabled
whenever a byte is written to one of the three key registers.
The output of the parity detection circuit is connected to
the
pin, as well as the state of this pin being reected by
the Status Register PAR (S3) bit. Status Register bit PAR goes
to “1” whenever a byte with even parity (an even number of
“1”s) is detected.
The Status Register also has a Latched
Parity bit (LPAR, S4) which is set to “1” whenever the Status
Register PAR bit goes to “1”. Once it is set to “1”, the LPAR
bit is not cleared until a reset occurs or a new Load Key
command is issued.
CP
PAR
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