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参数资料
| 型号： | CA95C09-10CT |
| 元件分类： | 加密电路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP44 |
| 封装： | TQFP-44 |
| 文件页数： | 16/42页 |
| 文件大小： | 180K |
| 代理商： | CA95C09-10CT |
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Tundra Semiconductor Corporation
CA95C68/18/09
Tundra Semiconductor Corporation
3-47
When an encrypted key has been loaded, the parity detect
logic operates only after the decrypted key is available. The
encrypted data is not checked for parity. The
signal will
reect the state of the decrypted bytes on a byte-to-byte basis,
as they are clocked through the parity check logic on their
way to the appropriate key register. Therefore, the time
indicates the status of a byte of decrypted key data may be as
short as four clock cycles. The LPAR bit in the Status Register
will indicate if any byte contained errors.
Data Flow
The Mode Register contains two bits, M2 and M3, which
control the ow of data into and out of the DCP through the
Master and Slave Ports. Three basic congurations are
provided: single port, and two dual port congurations.
Single Port Conguration
The simplest conguration occurs when the Mode Register
Data Flow Control bits are set to Master Port only. Data to be
encrypted/decrypted (depending on the value loaded into the
Encrypt/Decrypt bit (M4) of the Mode Register) is written to
the Input Register through the Master Port.
To facilitate
monitoring of the Input Register status, the
signal
goes LOW when the Input Register is not full. Clear or cipher
data is ready to be read by the host CPU through the Master
Port Output Register address when
goes LOW.
Therefore,
is redened as Master Input Flag and
is redened as Master Output Flag.
PAR
MFLG
SFLG
MFLG
SFLG
Figure 3-15 : CA95C68 and CA95C18 Data Flow Options
AUXILIARY
PORT
MASTER
KEY
COMMANDS
ENCRYPT AND DECRYPT
KEYS, CLEAR TEXT
CIPHER TEXT
8-BIT
CPU BUS
CA95C18
CA95C68
DCP
MASTER
PORT
AUXILIARY
PORT
MASTER
KEY
COMMANDS
ENCRYPT AND DECRYPT
KEYS, CLEAR OR CIPHER TEXT
8-BIT
CPU BUS
CA95C18
CA95C68
DCP
MASTER
PORT
CIPHER OR
CLEAR TEXT
PERIPHERAL
DEVICE OR
BUFFER
SLAVE
PORT
AUXILIARY
PORT
ENCRYPT AND DECRYPT
KEYS, CLEAR OR
CIPHER TEXT
8-BIT
CPU BUS
CA95C18
CA95C68
DCP
MASTER
PORT
CIPHER OR CLEAR
TEXT
PERIPHERAL
DEVICE OR
BUFFER
SLAVE
PORT
COMMANDS
AND STATUS
HIGH SPEED
INTERFACE
SINGLE-PORT CONFIGURATION
MULTIPLEXED CONTROL
DUAL-PORT CONFIGURATION
MULTIPLEXED CONTROL
DUAL-PORT CONFIGURATION
DIRECT CONTROL
Dual Port, Master Port Clear Conguration
In the dual port congurations, entering and removing data
is accomplished with both the Master and Slave Ports. In
the Master Port Clear conguration, clear text for
encryption or clear text resulting from decryption can pass
only through the Master Port. Cipher text can be handled
only through the Slave Port. The direction of data ow is
controlled either by the Encrypt/Decrypt bit (M4) in the
Mode Register, or by the Start Encryption or Start
Decryption commands. For encryption, clear data is written
through the Master Port to the Input Register, and cipher
data can be read from the Output Register through the Slave
Port at the appropriate time. If decryption is selected, the
process is reversed, cipher data being written to the Input
Register through the Slave Port, and the clear data being
read from the Output Register through the Master Port.
Dual Port, Slave Port Clear Conguration
This conguration is identical to the Dual Port, Master Port
Clear conguration described above, except that the
direction of ciphering is reversed. That is, all data written,
or read at the Master Port is cipher text, and all data at the
Slave Port is clear text
.
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