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参数资料
| 型号： | CA95C09-10CT |
| 元件分类： | 加密电路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP44 |
| 封装： | TQFP-44 |
| 文件页数： | 32/42页 |
| 文件大小： | 180K |
| 代理商： | CA95C09-10CT |
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CA95C68/18/09
Tundra Semiconductor Corporation
3-62
Tundra Semiconductor Corporation
COMMAND DESCRIPTION
All operations of the DCP result from command inputs,
which are entered in Multiplexed Control Mode by writing a
command byte to the Command Register. Command inputs
are entered in Direct Control Mode by raising and lowering
the logic levels on the AUX7- K/D, AUX6-E/D and AUX5-S/S
pins. Table 3-8 shows all commands that may be given in
Multiplexed Control Mode and Table 3-9 shows the subset
executable in Direct Control Mode.
Load Clear M Key Through Auxiliary Port (90H)
Load Clear E Key Through Auxiliary Port (91H)
Load Clear D Key Through Auxiliary Port (92H)
These commands override data ow specications set in the
Mode Register and cause the Master (M), Encrypt (E), or
Decrypt (D) Key Register to be loaded with eight bytes
written to the Auxiliary Port. Once the load command is
written to the Command Register, the Auxiliary Port ag
(
) pin will go active (LOW), as well as the Auxiliary
Port Flag bit (S2) in the Status Register being set to “1”,
indicating that the device is able to accept key bytes at the
Auxiliary Port bus. In addition, the Command Pending bit
(S6) will go to “1” during the entire loading process.
When data has been setup on the Auxiliary Port pins, each
byte is written by placing an active LOW signal on the
Auxiliary Port Strobe (
). The actual write occurs on
the rising edge of
. The Auxiliary Port Flag (
)
will go inactive immediately after the eighth strobe goes
active (LOW). However, the Command Pending bit (S6) will
remain “1” for several more clock cycles, until the key
loading process is completed. All key bytes are checked for
correct (odd) parity as they are entered.
Load Clear E Key Through Master Port (11H)
Load Clear D Key Through Master Port (12H)
These commands are available in both Multiplexed Control
and Direct Control Modes. They override the data ow
specications set in the Mode Register (bits M2 and M3) and
allow eight bytes of data to be written to the appropriate key
register through the Master Port. The input register must be
addressed before beginning to load the eight key bytes. In
Multiplexed Control Mode, the command is initiated by
writing the instruction to the Command Register. In Direct
Control Mode, the command is initiated by raising the
AUX7-K/D control input while the AUX5-S/S input is LOW
and the level on AUX6-E/D determines which key register is
loaded.
When the command has been recognized, the Command
Pending bit (S6 in the Status Register) will go to “1” and in
Direct Control Mode AUX3-
will go active (LOW),
indicating that key loading may proceed. The host system
then writes exactly eight bytes to the Input Register through
the Master Port. When the Key Register has been loaded, the
Command Pending bit will return to “0”, and in Direct
Control Mode the AUX3-
output will go inactive,
indicating that the DCP can accept the next command.
Load Encrypted E Key Through Auxiliary Port (B1H)
Load Encrypted D Key Through Auxiliary Port (B2H)
These commands are only available in Multiplexed Control
Mode. They are similar to the Load Clear E (or D) Key
through Auxiliary Port commands, except that key bytes are
initially decrypted using the Electronic Code Book algorithm
and the Master (M) Key. The key bytes then pass through the
parity checking logic and into the appropriate key register.
The Command Pending bit (S6) will be “1” during the entire
decrypt-and-load operation. The Busy bit (S5) will be “1”
during the actual decrypting of the key.
Load Encrypted E Key Through Master Port (31H)
Load Encrypted D Key Through Master Port (32H)
These commands (available in Multiplexed Control Mode
only) are similar in effect to Load Clear E (or D) Key
Through Master Port, except that key bytes are rst
decrypted using the Electronic Code Book algorithm and the
Master (M) Key. The bytes are then loaded into the target key
register, after having passed through the parity checking
logic.
The Command Pending bit (S6) will be “1” during the entire
decrypt-and-load operation. As well, the Busy bit (S5) will
be “1” during the actual decryption process.
AFLG
ASTB
AFLG
CP
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