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参数资料
| 型号： | CA95C09-10CT |
| 元件分类： | 加密电路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP44 |
| 封装： | TQFP-44 |
| 文件页数： | 34/42页 |
| 文件大小： | 180K |
| 代理商： | CA95C09-10CT |
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CA95C68/18/09
Tundra Semiconductor Corporation
3-28
Tundra Semiconductor Corporation
Table 3-2 : Pin Description
Symbol
95C68/18
95C09
TYPE
Name and Function
PDIP
PLCC
TQFP
CLK
14
15
16
10
I
Clock: An external timing source is input via this pin. The Master and Slave
Port data strobe signals (
,
for CA95C68 and
,
for CA95C18) must change synchronously with the clock input. In
Direct Control Mode the AUX5-S/S must also be synchronous. The output
ags for the three ports (
,
) will all change
synchronously with the clock.
C/K
13
14
–
I
Control/Key Mode Control:
This input controls the mode of operation of
the DCP. The DCP enters into Multiplexed Control Mode when a low input is
placed on the C/K pin, enabling programmed access to internal registers
through the Master Port and enabling input of keys through the Auxiliary
Port.
In Direct Control Mode (C/K HIGH), several of the Auxiliary Port pins
become direct control/status signals which can be driven/sensed by high-
speed controller logic, and access to internal registers through the Master
Port is limited to the Input and Output Registers.
DCM
–
15
9
I
Direct Control Mode: (For CA95C09) This input functions identical to the
C/K input. (See C/K pin description).
MP7 –
MP0
21-24
19-16
23-26
21-18
24-27
21-18
18-21
15-12
I/O
Master Port Bus: These eight bi-directional signals are used to input and
output data, as well as specify the internal register addresses in Multiplexed
Control Mode. The Master Port provides software access to the Status,
Command, Mode, Mask, Input and Output Registers. For the CA95C68, the
tri-state Master Port outputs will be enabled only when the Master Port is
selected by Master Port Chip Select (
) LOW, and when Master Port
Read (
) is strobed LOW. For the CA95C18, the Master Port outputs
are enabled when selected by
, and when MR/W is HIGH and
is LOW. MP0 is the low-order bit. Data and key information are entered into
this port with the most signicant byte rst.
25
27
28
22
I
Master Port Chip Select: This active LOW input signal is used to select the
Master Port. In Multiplexed Control Mode (C/K LOW), the level on
is
latched internally on the falling edge of Master Port Address Latch Enable
(MALE). This latched level is maintained as long as MALE is LOW; when
MALE is HIGH, the latch becomes transparent and the internal signal will
follow the
input. No latching of
occurs in Direct Control Mode
(C/K HIGH). The level on
is passed directly to the internal select
circuitry regardless of the state of Master Port Address Latch Enable
(MALE).
MWR
MRD
SDS
MDS
SDS
AFLG
MFLG
SFLG
MCS
MRD
MCS
MDS
MCS
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