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参数资料
| 型号： | CA95C09-10CT |
| 元件分类： | 加密电路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP44 |
| 封装： | TQFP-44 |
| 文件页数： | 19/42页 |
| 文件大小： | 180K |
| 代理商： | CA95C09-10CT |
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CA95C68/18/09
Tundra Semiconductor Corporation
3-50
Tundra Semiconductor Corporation
Command Register
Data written to the 8-bit, write only Command Register
through the Master Port is interpreted as an instruction. A
detailed description of each command is given in the
Command Description section, and the commands and their
binary representations are summarized in Table 3-8 and
Table 3-8 : Command Codes in Multiplexed Control Mode
Status Register
The bit assignments for the read-only Status Register are
shown in Figure 3-17. The PAR, AFLG, SFLG and MFLG
bits indicate the status of the similarly named output pins, as
do the Busy and Command Pending bits when the DCP is the
Direct Control Mode (C/K HIGH). In each case, the output
signal will be active LOW when the corresponding Status bit
is a “1”. The Parity bit indicates the parity of the most
recently entered key byte. The LPAR bit, on the other hand,
indicates whether any key byte with even parity has been
encountered since the last Reset or Load Key command.
Hex
Code
Command
90
91
92
11
12
Load Clear M Key through Auxiliary Port
Load Clear E Key through Auxiliary Port
Load Clear D Key through Auxiliary Port
Load Clear E Key through Master Port
Load Clear D Key through Master Port
B1
B2
31
32
Load Encrypted E Key through Auxiliary Port
Load Encrypted D Key through Auxiliary Port
Load Encrypted E Key through Master Port
Load Encrypted D Key through Master Port
85
84
A5
A4
Load Clear IVE through Master Port
Load Clear IVD through Master Port
Load Encrypted IVE through Master Port
Load Encrypted IVD through Master Port
8D
8C
A9
A8
Read Clear IVE through Master Port
Read Clear IVD through Master Port
Read Encrypted IVE through Master Port
Read Encrypted IVD through Master Port
39
41
40
C0
Encrypt with Master Key
Start Encryption
Start Decryption
Start
E0
00
Stop
Software Reset
Table 3-9 : Implicit Command Sequences in Direct
Control Mode
The Busy bit will be a “1” whenever the ciphering algorithm
unit is actively encrypting or decrypting data. For example,
the Busy bit is set in response to a Load Encrypted Key
command (the Command Pending bit will go HIGH as well)
or in the ciphering of regular text (indicated by the Start/Stop
bit being a “1”). If the ciphered data cannot be transferred to
the Output Register (due to the presence of data from a
previous ciphering cycle), then the Busy bit will remain a
“1”. The Busy bit will be “0” at all other times, including if
no ciphering is possible because no data has been loaded into
the Input Register.
The Command Pending bit is set to “1” by any instruction
which requires the transfer of data to or from a non-
addressable internal register, such as when writing key bytes
to the E Key Register or reading bytes from the IVE Register.
Therefore, the Command Pending bit will be set following
all commands except the three Start Commands, the Stop
command and the software Reset command. The Command
Pending bit will return to an inactive state (“0”) after all eight
bytes have been transferred following Load Clear, Read
Clear or Read Encrypted commands. In addition the inactive
state (“0”) only returns after data has been entered, decrypted
and placed into the desired register following Load
Encrypted commands.
The Start/Stop bit is set to “1” when one of the Start
commands is entered, and is reset to “0” whenever a reset
occurs or when a new command other than a Start is entered.
C/K
Aux7-
K/D
AUX6-
E/D
AUX5-
S/S
Command Initiated
HL
L
↑
Start Decryption
HL
H
↑
Start Encryption
HL
X
↓
Stop
H
↑
L
Load Clear D Key through
Master Port
H
↑
H
L
Load Clear E Key through
Master Port
H
↓
X
L
End Load Key Command
H
X
H
Not Allowed
L
Data
AUX Pins become Key byte
Inputs
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