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参数资料
| 型号： | CAT1022LI-45-G |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/20页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISR CPU 2K EEPROM 8PDIP |
| 标准包装： | 50 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 130 ms |
| 电压 - 阀值： | 4.5V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
CAT1021, CAT1022, CAT1023
Page Write
The CAT1021/22/23 writes up to 16 bytes of data in a
single write cycle, using the Page Write operation. The page
write operation is initiated in the same manner as the byte
write operation, however instead of terminating after the
initial byte is transmitted, the Master is allowed to send up
to 15 additional bytes. After each byte has been transmitted,
the CAT1021/22/23 will respond with an acknowledge and
internally increment the lower order address bits by one. The
high order bits remain unchanged.
S
T
If the Master transmits more than 16 bytes before sending
the STOP condition, the address counter ‘wraps around,’
and previously transmitted data will be overwritten.
When all 16 bytes are received, and the STOP condition
has been sent by the Master, the internal programming cycle
begins. At this point, all received data is written to the
CAT1021/22/23 in a single write cycle.
S
BUS ACTIVITY:
MASTER
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
T
O
P
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 8. Byte Write Timing
S
T
S
BUS ACTIVITY:
MASTER
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA?n
DATA n+1
T
DATA n+15 O
P
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 9. Page Write Timing
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is issued
to indicate the end of the host’s write opration, the
CAT1021/22/23 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issuing
the start condition followed by the slave address for a write
operation. If the device is still busy with the write operation,
no ACK will be returned. If a write operation has completed,
an ACK will be returned and the host can then proceed with
the next read or write operation.
WRITE PROTECTION PIN (WP)
The Write Protection feature (CAT1021 only) allows the
user to protect against inadvertent memory array
programming. If the WP pin is tied to V CC , the entire
memory array is protected and becomes read only. The
CAT1021 will accept both slave and byte addresses, but the
memory location accessed is protected from programming
by the device’s failure to send an acknowledge after the first
byte of data is received.
READ OPERATIONS
The READ operation for the CAT1021/22/23 is initiated
in the same manner as the write operation with one
operations are possible: Immediate/Current Address
READ, Selective/Random READ and Sequential READ.
exception, the R/W bit is set to one. Three different READ
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CAT1022LI-45-GT2 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer |
| CAT1022LI-45-GT3 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer |
| CAT1022LI-45T2 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer |
| CAT1022LI-45-T2 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer |
| CAT1022LI-45T3 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer |
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