- 您现在的位置：买卖IC网 > PDF目录16048 > CAT1161WI-42-T3 (ON Semiconductor)IC SUPERVISOR W/MEM 4.25V 8SOIC PDF资料下载
参数资料
| 型号： | CAT1161WI-42-T3 |
| 厂商： | ON Semiconductor |
| 文件页数： | 7/13页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR W/MEM 4.25V 8SOIC |
| 标准包装： | 1 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 高有效/低有效 |
| 复位超时： | 最小为 130 ms |
| 电压 - 阀值： | 4.25V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 标准包装 |
| 产品目录页面： | 806 (CN2011-ZH PDF) |
| 其它名称： | CAT1161WI-42-T3DKR |
CAT1161, CAT1162
FUCTIONAL DESCRIPTION
The CAT1161/2 supports the I 2 C Bus data transmission
protocol. This Inter ? Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter and
any device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the serial
clock and all START and STOP conditions for bus access.
Both the Master device and Slave device can operate as
either transmitter or receiver, but the Master device controls
which mode is activated.
I 2 C Bus Protocol
The features of the I 2 C bus protocol are defined as
follows:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT1161/2 monitors the SDA and
SCL lines and will not respond until this condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
The Master begins a transmission by sending a START
condition. The Master sends the address of the particular
slave device it is requesting. The four most significant bits
of the 8 ? bit slave address are fixed as 1010.
The next three bits (Figure 6) define memory addressing.
For the CAT1161/2 the three bits define higher order bits.
The last bit of the slave address specifies whether a Read
or Write operation is to be performed. When this bit is set to
1, a Read operation is selected, and when set to 0, a Write
operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT1161/2 monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matches the transmitted slave address. The CAT1161/2 then
performs a Read or Write operation depending on the
R/W bit.
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
STA RT
Figure 5. Acknowledge Timing
ACKNOWLEDGE
CAT1161/2
1
0
1
0
a10
a9
a8
R/W
Note: a8, a9 and a10 correspond to the address of the memory array address word.
Figure 6. Slave Address Bits
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
The CAT1161/2 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8 ? bit
byte.
When the CAT1161/2 begins a READ mode it transmits
8 bits of data, releases the SDA line and monitors the line for
an acknowledge. Once it receives this acknowledge, the
CAT1161/2 will continue to transmit data. If no
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition.
http://onsemi.com
7
相关PDF资料 |
PDF描述 |
|---|---|
| 200PX33MEFCT810X20 | CAP ALUM 33UF 200V 20% RADIAL |
| VE-JV2-EZ-F2 | CONVERTER MOD DC/DC 15V 25W |
| CCK26.5-MM-190-48 | RFCABLE M/M LOW LOSS 26.5GHZ 48" |
| RCC25DRYN | CONN EDGECARD 50POS DIP .100 SLD |
| LHL10NB393J | INDUCTOR 39000UH 53MA RADIAL |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CAT1161WI45 | 功能描述:监控电路 16K I2C Memory w/WDT RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| CAT1161WI-45 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT1161WI-45-G | 功能描述:监控电路 CPU w/16K RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| CAT1161WI-45-GT3 | 功能描述:监控电路 CPU w/16K RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| CAT1161WI-45-T3 | 功能描述:监控电路 CPU Supervisor with 16K EEPROM RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。