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参数资料
| 型号： | CAT24C128HU3IGT3 |
| 厂商： | ON Semiconductor |
| 文件页数： | 7/16页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM SERIAL 128KB I2C 8UDFN |
| 标准包装： | 3,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 128K (16K x 8) |
| 速度： | 400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-UFDFN 裸露焊盘 |
| 供应商设备封装： | 8-UDFN（2x3） |
| 包装： | 带卷 (TR) |
CAT24C128
Write Operations
Byte Write
Upon receiving a Slave address with the R/W bit set to ‘0’,
the CAT24C128 will interpret the next two bytes as address
bytes. These bytes are used to initialize the internal address
counter; the 2 most significant bits are ‘don’t care’, the next
8 point to one of 256 available pages and the last 6 point to
a location within a 64 byte page. A byte following the
address bytes will be interpreted as data. The data will be
loaded into the Page Write Buffer and will eventually be
written to memory at the address specified by the 14 active
address bits provided earlier. The CAT24C128 will
acknowledge the Slave address, address bytes and data byte.
The Master then starts the internal Write cycle by issuing a
STOP condition (Figure 6). During the internal Write cycle
(t WR ), the SDA output will be tri ? stated and additional Read
or Write requests will be ignored (Figure 7).
Page Write
By continuing to load data into the Page Write Buffer after
the 1 st data byte and before issuing the STOP condition, up
to 64 bytes can be written simultaneously during one
internal Write cycle (Figure 8). If more data bytes are loaded
than locations available to the end of page, then loading will
continue from the beginning of page, i.e. the page address is
latched and the address count automatically increments to
and then wraps ? around at the page boundary. Previously
loaded data can thus be overwritten by new data. What is
eventually written to memory reflects the latest Page Write
Buffer contents. Only data loaded within the most recent
Page Write sequence will be written to memory.
Acknowledge Polling
The ready/busy status of the CAT24C128 can be
ascertained by sending Read or Write requests immediately
following the STOP condition that initiated the internal
Write cycle. As long as internal Write is in progress, the
CAT24C128 will not acknowledge the Slave address.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the CAT24C128. The state of the WP pin is strobed on the
last falling edge of SCL immediately preceding the first data
byte (Figure 9). If the WP pin is HIGH during the strobe
interval, the CAT24C128 will not acknowledge the data byte
and the Write request will be rejected.
Delivery State
The CAT24C128 is shipped erased, i.e., all bytes are FFh.
BUS ACTIVITY:
MASTER
S
T
A
R
T
SLAVE
ADDRESS
ADDRESS
BYTE
a 13 ? a 8
ADDRESS
BYTE
a 7 ? a 0
DATA
BYTE
S
T
O
P
S
* *
P
SLAVE
A
C
K
A
C
K
A
C
K
A
C
K
* = Don’t Care Bit
Figure 6. Byte Write Sequence
SCL
SDA
8th Bit
Byte n
ACK
t WR
STOP
CONDITION
Figure 7. Write Cycle Timing
http://onsemi.com
7
START
CONDITION
ADDRESS
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CAT24C128HU3I-GT3 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT24C128HU4IGT3 | 功能描述:电可擦除可编程只读存储器 DPPNV32TAPSUP/DOWN RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| CAT24C128LGI | 制造商:Catalyst Semiconductor 功能描述: |
| CAT24C128LI-G | 功能描述:电可擦除可编程只读存储器 (16384x8) 128K RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| CAT24C128UI-G | 制造商:ON Semiconductor 功能描述: |
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