参数资料
| 型号： | CAT25256VI-G |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/20页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 256KBIT 10MHZ 8SOIC |
| 标准包装： | 100 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 256K (32K x 8) |
| 速度： | 10MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
| 产品目录页面： | 808 (CN2011-ZH PDF) |
CAT25256
READ OPERATIONS
Read from Memory Array
To read from memory, the host sends a READ instruction
followed by a 16 ? bit address (see Table 14 for the number
of significant address bits).
After receiving the last address bit, the CAT25256 will
respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS high.
Read Identification Page
Reading the additional 64 ? byte Identification Page (IP) is
achieved using the same Read command sequence as used
for Read from main memory array (Figure 9). The IPL bit
from the Status Register must be set (IPL = 1) before
attempting to read from the IP. The [A5:A0] are the address
significant bits that point to the data byte shifted out on the
SO pin. If the CS continues to be held low, the internal
CS
address register defined by [A5:A0] bits is automatically
incremented and the next data byte from the IP is shifted out.
The byte address must not exceed the 64 ? byte page
boundary.
Read Status Register
To read the status register, the host simply sends a RDSR
command. After receiving the last bit of the command, the
CAT25256 will shift out the contents of the status register on
the SO pin (Figure 10). The status register may be read at
any time, including during an internal write cycle. While the
internal write cycle is in progress, the RDSR command will
output the full content of the status register (New product,
Rev. E) or the RDY (Ready) bit only (i.e., data out = FFh) for
previous product revisions C, D (Mature product). For easy
detection of the internal write cycle completion, both during
writing to the memory array and to the status register, we
recommend sampling the RDY bit only through the polling
routine. After detecting the RDY bit “0”, the next RDSR
instruction will always output the expected content of the
status register.
0
1
2
3
4
5
6
7
8
9
10
20 21
22 23
24
25
26 27
28 29
30
SCK
OPCODE
BYTE ADDRESS*
SI
0
0
0
0
0
0
1
1
A N
A 0
SO
HIGH IMPEDANCE
7
6
5
DATA OUT
4 3 2
1
0
CS
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 14)
Figure 9. READ Timing
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCK
OPCODE
SI
0
0
0
0
0
1
0
1
SO
HIGH IMPEDANCE
7
6
5
4
DATA OUT
3
2
1
0
Dashed Line = mode (1, 1)
MSB
Figure 10. RDSR Timing
http://onsemi.com
11
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CAT25256VI-G | 制造商:ON Semiconductor 功能描述:IC EEPROM 256KBIT SERIAL 10MHZ SOIC-8 |
| CAT25256VI-GT3 | 功能描述:电可擦除可编程只读存储器 256K SPI Serial CMOS 电可擦除可编程只读存储器 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| CAT25256XE | 制造商:ON Semiconductor 功能描述: |
| CAT25256XE-T2 | 制造商:ON Semiconductor 功能描述:256KB SPI SER CMOS EEPROM - Tape and Reel |
| CAT25256XI | 功能描述:电可擦除可编程只读存储器 (32kx8) 256K SPI 1.8 to 5.5V RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
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