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参数资料
| 型号： | CAT28LV65WI25 |
| 厂商： | ON Semiconductor |
| 文件页数： | 6/15页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 64KBIT 250NS 28SOIC |
| 产品变化通告： | Product Discontinuation 30/Sept/2011 |
| 标准包装： | 27 |
| 格式 - 存储器： | EEPROMs - 并行 |
| 存储器类型： | EEPROM |
| 存储容量： | 64K (8K x 8) |
| 速度： | 250ns |
| 接口： | 并联 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 管件 |
| 其它名称： | 28LV65WI-25 CAT28LV65WI-25 CAT28LV65WI-25-ND |
CAT28LV65
DEVICE OPERATION
Read
Data stored in the CAT28LV65 is transferred to the data
bus when WE is held high, and both OE and CE are held low.
The data bus is set to a high impedance state when either CE
or OE goes high. This 2 ? line control architecture can be used
to eliminate bus contention in a system environment.
t RC
ADDRESS
t CE
CE
t OE
OE
Byte Write
A write cycle is executed when both CE and WE are l ow,
and OE is high. Write cycles can be initiated using either WE
or CE, with the address input being latched on the falling
edge of WE or CE, whichever occurs last. Data, conversely,
is latched on the rising edge of WE or CE, whichever occurs
first. Once initiated, a byte write cycle automatically erases
the addressed byte and the new data is written within 5 ms.
WE
DATA OUT
V IH
HIGH ? Z
t LZ
t OLZ
t AA
t OH
DATA VALI D
t OHZ
t HZ
DATA VALID
Figure 4. Read Cycle
t WC
ADDRESS
t AS
t AH
CE
OE
WE
t OES
t CS
t WP
t CH
t OEH
RDY/BUSY
DATA OUT
DATA IN
HIGH ? Z
t RB
HIGH ? Z
DATA VALID
t BLC
HIGH ? Z
t DS
t DH
Figure 5. Byte Write Cycle [WE Controlled]
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CAT28LV65WI-25 | 制造商:Catalyst Semiconductor 功能描述: |
| CAT28LV65WI-25T | 功能描述:电可擦除可编程只读存储器 64K-Bit CMOS PARA 电可擦除可编程只读存储器 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| CAT28LV65XI-15 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT30/41316L | 制造商:MISCELLANEOUS 功能描述: |
| CAT-3000-01 | 制造商:Samtec Inc 功能描述:CAT - Bulk |
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