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参数资料
| 型号： | CAT34AC02RE-1.8TE13 |
| 英文描述： | 2K-Bit SMBus EEPROM for ACR Card Configuration |
| 中文描述： | 的2K位的SMBus对于ACR卡的EEPROM配置 |
| 文件页数： | 5/10页 |
| 文件大小： | 68K |
| 代理商： | CAT34AC02RE-1.8TE13 |
CAT34AC02
5
Doc No. 1025, Rev. E
SERIAL BUS PROTOCOL
The following defines the features of the ACR Serial bus
protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT34AC02 monitor the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master then sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1011 for the CAT34AC02 (see Fig. 5). The next three
significant bits (A2, A1, A0) are the device address bits
and define which device the Master is accessing. Up to
eight CAT34AC02 may be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT34AC02 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT34AC02 then performs a Read or a Write operation
depending on the state of the R/
W
bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
The CAT34AC02 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
byte.
When the CAT34AC02 begins a READ mode, it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT34AC02 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
Figure 4. Acknowledge Timing
Figure 5. Slave Address Bits
1
DEVICE ADDRESS
0
1
1
A2
A1
A0
R/W
ACKNOWLEDGE
1
START
SCL FROM
MASTER
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
相关PDF资料 |
PDF描述 |
|---|---|
| CAT34AC02UA-1.8 | 2K-Bit SMBus EEPROM for ACR Card Configuration |
| CAT34AC02UA-1.8TE13 | 2K-Bit SMBus EEPROM for ACR Card Configuration |
| CAT34AC02UA-TE13 | 2K-Bit SMBus EEPROM for ACR Card Configuration |
| CAT34AC02YI-1.8TE13 | 2K-Bit SMBus EEPROM for ACR Card Configuration |
| CAT34AC02YI-TE13 | 2K-Bit SMBus EEPROM for ACR Card Configuration |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CAT34AC02RE-TE13 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:2K-Bit SMBus EEPROM for ACR Card Configuration |
| CAT34AC02RI | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:2K-Bit SMBus EEPROM for ACR Card Configuration |
| CAT34AC02RI-1.8 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:2K-Bit SMBus EEPROM for ACR Card Configuration |
| CAT34AC02RI-1.8TE13 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:2K-Bit SMBus EEPROM for ACR Card Configuration |
| CAT34AC02RI-TE13 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:2K-Bit SMBus EEPROM for ACR Card Configuration |
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