参数资料
型号: CAT93C66YI-G
厂商: ON Semiconductor
文件页数: 6/16页
文件大小: 0K
描述: IC EEPROM 4KB 2MHZ 8-TSSOP
标准包装: 100
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 4K(512 x 8 或 256 x 16)
速度: 2MHz
接口: Microwire 3 线串行
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 8-TSSOP
包装: 管件
CAT93C66, CAT93W66
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C66,
CAT93W66 will come out of the high impedance state and,
after sending an initial dummy zero bit, will begin shifting
out the data addressed (MSB first). The output data bits will
toggle on the rising edge of the SK clock and are stable after
the specified time delay (t PD0 or t PD1 ).
For the CAT93C66, CAT93W66 after the initial data word
has been shifted out and CS remains asserted with the SK
clock continuing to toggle, the device will automatically
increment to the next address and shift out the next data word
in a sequential READ mode. As long as CS is continuously
asserted and SK continues to toggle, the device will keep
incrementing to the next address automatically until it
reaches to the end of the address space, then loops back to
address 0. In the sequential READ mode, only the initial data
word is preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit. The READ
instruction timing is illustrated in Figure 3.
Erase/Write Enable and Disable
The device powers up in the write disable state. Any
writing after power ? up or after an EWDS (erase/write
disable) instruction must first be preceded by the EWEN
(erase/write enable) instruction. Once the write instruction
is enabled, it will remain enabled until power to the device
is removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93C66,
CAT93W66 write and erase instructions, and will prevent
any accidental writing or clearing of the device. Data can be
read normally from the device regardless of the write
enable/disable status. The EWEN and EWDS instructions
timing is shown in Figure 4.
SK
t DIS
t SKHI
t SKLOW
t DIH
t CSH
DI
CS
t CSS
VALID
VALID
SK
CS
DO
t DIS
Figure 2. Synchronous Data Timing
t PD0 , t PD1
DATA VALID
t CSMIN
A N
A N ? 1
A 0
Don’t Care
DI
1
1
0
t PD0
DO
HIGH ? Z
Dummy 0
D 15 . . . D 0
or
D 7 . . . D 0
Address + 1
D 15 . . . D 0
or
D 7 . . . D 0
Address + 2
D 15 . . . D 0
or
D 7 . . . D 0
Address + n
D 15 . . .
or
D 7 . . .
Figure 3. READ Instruction Timing
http://onsemi.com
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