参数资料
| 型号： | CAV24C02WE-GT3 |
| 厂商： | ON Semiconductor |
| 文件页数： | 3/11页 |
| 文件大小： | 0K |
| 描述： | EEPROM I2C SER 2KB I2C 8SOIC |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 2K (256 x 8) |
| 速度： | 100kHz，400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 标准包装 |
| 其它名称： | CAV24C02WE-GT3OSDKR |
CAV24C02, CAV24C04, CAV24C08, CAV24C16
Table 4. PIN IMPEDANCE CHARACTERISTICS ( V CC = 2.5 V to 5.5 V, T A = ? 40 ° C to +125 ° C, unles s otherwise specified.)
Symbol
C IN (Note 4)
I WP (Note 5)
Parameter
SDA Pin Capacitance
Other Pins
WP Input Current
Conditions
V IN = 0 V, f = 1.0 MHz, V CC = 5.0 V
V IN < V IH , V CC = 5.5 V
Max
8
6
130
Units
pF
pF
m A
V IN < V IH , V CC = 3.6 V
V IN < V IH , V CC = 2.5 V
V IN > V IH
120
80
2
I A (Note 5)
Address Input Current
(A0, A1, A2)
V IN < V IH , V CC = 5.5 V
V IN < V IH , V CC = 3.6 V
50
35
m A
V IN < V IH , V CC = 2.5 V
V IN > V IH
25
2
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC ? Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull ? down is relatively
strong; therefore the external driver must be able to supply the pull ? down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V CC ), the strong pull ? down reverts to a weak current source.
Table 5. A.C. C HARACTERISTICS (Note 6) (V CC = 2.5 V to 5.5 V, T A = ? 40 ° C to +125 ° C, unless otherwise specified.)
Standard
Fast
Symbol
Parameter
Min
Max
Min
Max
Units
F SCL
t HD:STA
t LOW
t HIGH
t SU:STA
t HD:DAT
t SU:DAT
t R
t F (Note 6)
t SU:STO
t BUF
t AA
t DH
T i (Note 6)
t SU:WP
t HD:WP
t WR
t PU (Notes 7, 8)
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power ? up to Ready Mode
4
4.7
4
4.7
0
250
4
4.7
100
0
2.5
100
1000
300
3.5
100
5
0.1
0.6
1.3
0.6
0.6
0
100
0.6
1.3
100
0
2.5
400
300
300
0.9
100
5
0.1
kHz
m s
m s
m s
m s
m s
ns
ns
ns
m s
m s
m s
ns
ns
m s
m s
ms
ms
6. Test conditions according to “AC Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t PU is the delay between the time V CC is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITIONS
Input Drive Levels
Input Rise and Fall Time
Input Reference Levels
Output Reference Level
Output Test Load
0.2 x V CC to 0.8 x V CC
v 50 ns
0.3 x V CC , 0.7 x V CC
0.5 x V CC
Current Source I OL = 3 mA; C L = 100 pF
http://onsemi.com
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| CAV24C02YE-GT3 | 功能描述:电可擦除可编程只读存储器 2KB I2C SER 电可擦除可编程只读存储器 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| CAV24C04 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:2-Kb, 4-Kb, 8-Kb and 16-Kb I2C CMOS Serial EEPROM |
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