参数资料
| 型号： | CAV24C02WE-GT3 |
| 厂商： | ON Semiconductor |
| 文件页数： | 4/11页 |
| 文件大小： | 0K |
| 描述： | EEPROM I2C SER 2KB I2C 8SOIC |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 2K (256 x 8) |
| 速度： | 100kHz，400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 标准包装 |
| 其它名称： | CAV24C02WE-GT3OSDKR |
CAV24C02, CAV24C04, CAV24C08, CAV24C16
Power ? On Reset (POR)
Each CAV24Cxx* incorporates Power ? On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state.
A CAV24Cxx device will power up into Standby mode
after V CC exceeds the POR trigger level and will power
down into Reset mode when V CC drops below the POR
trigger level. This bi ? directional POR feature protects the
device against ‘brown ? out’ failure following a temporary
loss of power.
*For common features, the CAV24C02/04/08/16 will be
referred to as CAV24Cxx.
Pin Description
SCL : The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA : The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A0, A1 and A2 : The Address inputs set the device address
when cascading multiple devices. When not driven, these
pins are pulled LOW internally.
WP : The Write Protect input pin inhibits all write
operations, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
Functional Description
The CAV24Cxx supports the Inter ? Integrated Circuit
(I 2 C) Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAV24Cxx acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver.
I 2 C Bus Protocol
The I 2 C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V CC supply via pull ? up
resistors. Master and Slave devices connect to the 2 ? wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see AC Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is high. An SDA transition while SCL is
high will be interpreted as a START or STOP condition
(Figure 2). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wake ? up’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8 ? bit
serial Slave address. For normal Read/Write operations, the
first 4 bits of the Slave address are fixed at 1010 (Ah). The
next 3 bits are used as programmable address bits when
cascading multiple devices and/or as internal address bits.
The last bit of the slave address, R/W, specifies whether a
Read (1) or Write (0) operation is to be performed. The 3
address space extension bits are assigned as illustrated in
Figure 3. A 2 , A 1 and A 0 must match the state of the external
address pins, and a 10 , a 9 and a 8 are internal address bits.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9th clock cycle (Figure 4). The Slave will also
acknowledge the address byte and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9 th clock cycle. As
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 5.
http://onsemi.com
4
相关PDF资料 |
PDF描述 |
|---|---|
| A42MX16-2VQG100I | IC FPGA MX SGL CHIP 24K 100-VQFP |
| HSC49DRYH-S13 | CONN EDGECARD 98POS .100 EXTEND |
| 951-015-010R011 | BACKSHELL 15POS 60DEG PLASTIC |
| ABC49DRYN-S13 | CONN EDGECARD 98POS .100 EXTEND |
| ABC49DRYH-S13 | CONN EDGECARD 98POS .100 EXTEND |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CAV24C02YE-GT3 | 功能描述:电可擦除可编程只读存储器 2KB I2C SER 电可擦除可编程只读存储器 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| CAV24C04 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:2-Kb, 4-Kb, 8-Kb and 16-Kb I2C CMOS Serial EEPROM |
| CAV24C04WE-GT3 | 功能描述:电可擦除可编程只读存储器 4KB I2C SER 电可擦除可编程只读存储器 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| CAV24C04YE-GT3 | 功能描述:电可擦除可编程只读存储器 4KB I2C SER 电可擦除可编程只读存储器 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| CAV24C08 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:2-Kb, 4-Kb, 8-Kb and 16-Kb I2C CMOS Serial EEPROM |
发布紧急采购，3分钟左右您将得到回复。